Shuang Liu

Orcid: 0000-0002-0587-4415

Affiliations:
  • University of Electronic Science and Technology of China, State Key Laboratory of Thin Solid Films and Integrated Devices, Chengdu, China


According to our database1, Shuang Liu authored at least 13 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A multi-synaptic memristor-based neural network and its encryption application.
Microelectron. J., 2026

A row- and column-individually programmable logic-in-memory macro using memristor-based non-volatile SRAM.
Microelectron. J., 2026

A 1-GHz frequency generator with high performance based on a 500-MHz high fundamental frequency quartz resonator.
IEICE Electron. Express, 2026

2025
A Neural Network-Based Real-time Casing Collar Recognition System for Downhole Instruments.
CoRR, December, 2025

A 2T1MTJ-Based In-Memory Computing Macro With Time-Domain Accumulation and Ramp-Type Readout.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

Casing Collar Identification using AlexNet-based Neural Networks for Depth Measurement in Oil and Gas Wells.
CoRR, November, 2025

Realization of Precise Perforating Using Dynamic Threshold and Physical Plausibility Algorithm for Self-Locating Perforating in Oil and Gas Wells.
CoRR, September, 2025

2024
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
IEEE J. Solid State Circuits, February, 2024

Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network.
Microelectron. J., 2024

Live Demonstration for Input-Sparsity-Aware RRAM Processing-in-Memory Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.
IEEE Trans. Biomed. Circuits Syst., February, 2023

FuzzJIT: Oracle-Enhanced Fuzzing for JavaScript Engine JIT Compiler.
Proceedings of the 32nd USENIX Security Symposium, 2023

A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology.
Proceedings of the International Conference on Electronics, 2023


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