Yang Liu

According to our database, Yang Liu authored at least 32 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Fullerene-Inspired Efficient Neuromorphic Network-on-Chip Scheme.

Pujun Zhou, Qi Yu, M. Chen, Guanchao Qiao, Yue Zuo, Zhong Zhang, Yang Liu, Shaogang Hu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.

Junjie Wang, Teng Zhang, Shuang Liu, Yihe Liu, Yuancong Wu, Shaogang Hu, Tupei Chen, Yang Liu, Yuchao Yang, Ru Huang

IEEE J. Solid State Circuits, February, 2024

2023

Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth.

Pujun Zhou, Yue Zuo, Guanchao Qiao, C. M. Zhang, Zhong Zhang, Liwei Meng, Qi Yu, Yang Liu, Shaogang Hu

IEEE Trans. Biomed. Circuits Syst., December, 2023

An efficient pruning and fine-tuning method for deep spiking neural network.

Liwei Meng, Guanchao Qiao, X. Y. Zhang, J. Bai, Yue Zuo, Pujun Zhou, Yang Liu, Shaogang Hu

Appl. Intell., December, 2023

An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.

Shuang Liu, Junjie Wang, Jingtao Zhou, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu

IEEE Trans. Biomed. Circuits Syst., February, 2023

FPGA-implemented Memristor-based Transient Chaotic Neural Network for AES Edge Encryption.

Hongzhe Wang, Kunsong Liu, Yi'an Liu, Junjie Wang, Mingyuan Sun, Kai Tang, Guohui Ren, Xindi Zhao, Yang Liu

Proceedings of the International Conference on Electronics, 2023

A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology.

Yihe Liu, Junjie Wang, Shuang Liu, Mingyuan Sun, Kai Tang, Guohui Ren, Xindi Zhao, Mingliang Sun, Yang Liu

Proceedings of the International Conference on Electronics, 2023

2022

A Co-Designed Neuromorphic Chip With Compact (17.9K F²) and Weak Neuron Number-Dependent Neuron/Synapse Modules.

Shaogang Hu, Guanchao Qiao, X. K. Liu, Y. H. Liu, C. M. Zhang, Yue Zuo, Pujun Zhou, Yian Liu, Ning Ning, Qi Yu, Yang Liu

IEEE Trans. Biomed. Circuits Syst., December, 2022

2021

Design of a constant loop bandwidth phase-locked loop based on artificial neural network.

Rui Guo, Yuancong Wu, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu

IEICE Electron. Express, 2021

2020

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC.

Jian Luo, Yang Liu, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Qi Yu

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Application of Deep Compression Technique in Spiking Neural Network Chip.

Yanchen Liu, Kun Qian, Shaogang Hu, Kun An, Sheng Xu, Xitong Zhan, Junjie Wang, Rui Guo, Yuancong Wu, Tupei Chen, Qi Yu, Yang Liu

IEEE Trans. Biomed. Circuits Syst., 2020

An energy-efficient deep convolutional neural networks coprocessor for multi-object detection.

Yuancong Wu, Junjie Wang, Kun Qian, Yanchen Liu, Rui Guo, Shaogang Hu, Qi Yu, Tupei Chen, Yang Liu, Limei Rong

Microelectron. J., 2020

Design of AM Self-Capacitive Transparent Touch Panel Based on a-IGZO Thin-Film Transistors.

Kejun Wu, Jun Zhang, Yuanbo Li, Xiangzhan Wang, Yang Liu, Qi Yu, Tupei Chen

IEEE Access, 2020

2019

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters.

Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu

J. Circuits Syst. Comput., 2019

A Neuromorphic-Hardware Oriented Bio-Plausible Online-Learning Spiking Neural Network Model.

Chunming Qiao, Shaogang Hu, Junjie Wang, C. M. Zhang, Tupei Chen, Ning Ning, Qi Yu, Yang Liu

IEEE Access, 2019

Implementation of a Low Noise Amplifier With Self-Recovery Capability.

Yanchen Liu, Caizhi Zhang, Tupei Chen, Deyu Kong, Rui Guo, Junjie Wang, Yuancong Wu, Shaogang Hu, L. M. Rong, Qi Yu, Yang Liu

IEEE Access, 2019

Study of Recall Time of Associative Memory in a Memristive Hopfield Neural Network.

Deyu Kong, Shaogang Hu, Junjie Wang, Zhen Liu, Tupei Chen, Qi Yu, Yang Liu

IEEE Access, 2019

Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range.

Rui Guo, Kun Qian, Jinping Wei, Tupei Chen, Yanchen Liu, Deyu Kong, Junjie Wang, Yuancong Wu, Shaogang Hu, Qi Yu, Yang Liu

IEEE Access, 2019

A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC.

Jian Luo, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Yang Liu, Qi Yu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS.

Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu

IEEE Trans. Very Large Scale Integr. Syst., 2018

Predicting House Price With a Memristor-Based Artificial Neural Network.

Junjie Wang, Shaogang Hu, X. T. Zhan, Q. Luo, Qi Yu, Zhen Liu, Tupei Chen, Y. Yin, Sumio Hosaka, Yang Liu

IEEE Access, 2018

The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction.

Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu

IEEE Access, 2018

Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network.

Deyu Kong, Shaogang Hu, Yuancong Wu, Junjie Wang, Canlong Xiong, Qi Yu, Zhengyu Shi, Zhen Liu, Tupei Chen, You Yin, Sumio Hosaka, Yang Liu

IEEE Access, 2018

2015

A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors.

Zhentao Xu, Wei Wang, Ning Ning, Wei Meng Lim, Yang Liu, Qi Yu

IEEE Trans. Very Large Scale Integr. Syst., 2015

Total ionizing dose sensitivity of function blocks in FRAM.

Ke Gu, Juin J. Liou, Wei Li, Yang Liu, Ping Li

Microelectron. Reliab., 2015

2014

A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs.

Jing Li, Shuangyi Wu, Yang Liu, Ning Ning, Qi Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A dithering Technique for Sha_less Pipelined ADC.

Ning Ning, Ling Du, Hua Chen, Shuangyi Wu, Qi Yu, Yang Liu

J. Circuits Syst. Comput., 2014

Digital Background Calibration for Timing skew in Time-Interleaved ADC.

Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu

J. Circuits Syst. Comput., 2014

A digital background calibration technique for SAR ADC based on capacitor swapping.

Ling Du, Ning Ning, Shuangyi Wu, Qi Yu, Yang Liu

IEICE Electron. Express, 2014

A 10-bit 100MS/s subrange SAR ADC with time-domain quantization.

Ling Du, Shuangyi Wu, Min Jiang, Ning Ning, Qi Yu, Yang Liu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure.

Zhentao Xu, X. L. Zhang, J. Z. Chen, Shaogang Hu, Qi Yu, Yang Liu, Wei Meng Lim

J. Circuits Syst. Comput., 2013

A process variation insensitive bandgap reference with self-calibration technique.

Ling Du, Ning Ning, Kejun Wu, Yang Liu, Qi Yu

Proceedings of the IEEE 10th International Conference on ASIC, 2013