# Shuzo Yajima

According to our database

^{1}, Shuzo Yajima## Awards

## IEEE Fellow

IEEE Fellow 2001, "For contributions to the development of computers and the theory of logic circuits.".

## Timeline

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Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2001

Tree-shellability of Boolean functions.

Theor. Comput. Sci., 2001

2000

Hardness of identifying the minimum ordered binary decision diagram.

Discrete Applied Mathematics, 2000

1998

Optimizing OBDDs Is Still Intractable for Monotone Functions.

Proceedings of the Mathematical Foundations of Computer Science 1998, 1998

1997

Size of Ordered Binary Decision Diagrams Representing Threshold Functions.

Theor. Comput. Sci., 1997

Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.

IEEE Trans. Computers, 1997

O(n)-Depth Modular Exponentiation Circuit Algorithm.

IEEE Trans. Computers, 1997

Exponential Lower Bounds on the Size of OBDDs Representing Integer Divistion.

Proceedings of the Algorithms and Computation, 8th International Symposium, 1997

Size and Variable Ordering of OBDDs Representing Treshold Functions.

Proceedings of the Computing and Combinatorics, Third Annual International Conference, 1997

1996

Square Rooting by Iterative Multiply-Additions.

Inf. Process. Lett., 1996

1995

Efficient construction of binary moment diagrams for verifying arithmetic circuits.

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

O(n)-depth circuit algorithm for modular exponentiation.

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994

Fault simulation for multiple faults by Boolean function manipulation.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Circuit complexity of slice functions and homogeneous functions.

Systems and Computers in Japan, 1994

On the Size of Ordered Binary Decision Diagrams Representing Threshold Functions.

Proceedings of the Algorithms and Computation, 5th International Symposium, 1994

1993

The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams.

Proceedings of the Algorithms and Computation, 4th International Symposium, 1993

Breadth-first manipulation of very large binary-decision diagrams.

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Infinity-Regular Temporal Logic and its Model Checking Problem.

Theor. Comput. Sci., 1992

Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem.

IEEE Trans. Computers, 1992

Linear time fault simulation algorithm using a content addressable memory.

Proceedings of the conference on European design automation, 1992

Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic.

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991

Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation.

IEEE Trans. Computers, 1991

An on-line error-detectable high-speed array divider.

Systems and Computers in Japan, 1991

Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets.

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Minimazation of Binary Decision Diagrams Based on Exchanges of Variables.

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing.

Proceedings of the 28th Design Automation Conference, 1991

Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits.

Proceedings of the 28th Design Automation Conference, 1991

Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.

Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic.

Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

1990

Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.

Proceedings of the Computer-Aided Verification, 1990

Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation.

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram.

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.

Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits.

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Algebraic Specification of Parallel Systems Based on Binary Relations between Events.

Systems and Computers in Japan, 1988

An on-line error-detectable array divider with a redundant binary representation and a residue code.

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

Parallel Computational Complexity of Logic Programs and Alternating Turing Machines.

FGCS, 1988

1987

High-Speed Logic Simulation on Vector Processors.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic.

IEEE Trans. Computers, 1987

On high-speed parallel algorithms using redundant coding.

Systems and Computers in Japan, 1987

A hardware algorithm for computing sine and cosine using redundant binary representation.

Systems and Computers in Japan, 1987

Description and verification of input constraints and input-output specifications of logic circuits.

Systems and Computers in Japan, 1987

1986

Hardware algorithms for computing exponentials and logarithms using redundant binary representation.

Systems and Computers in Japan, 1986

A square root hardware algorithm using redundant binary representation.

Systems and Computers in Japan, 1986

1985

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.

IEEE Trans. Computers, 1985

1984

Hardware Algorithms for VLSI Systems.

Proceedings of the VLSI Engineering: Beyond Software Engineering, 1984

1982

The Parallel Enumeration Sorting Scheme for VLSI.

IEEE Trans. Computers, 1982

A Longest Common Subsequence Algorithm Suitable for Similar Text Strings.

Acta Inf., 1982

Query Processing for Distributed Databases Using Generalized Semi-Joins.

Proceedings of the 1982 ACM SIGMOD International Conference on Management of Data, 1982

Hardware Algorithms and Logic Design Automation. An Overview and Progress Report.

Proceedings of the RIMS Symposium on Software Science and Engineering, 1982

An Interactive Simulation System for structured logic design - ISS.

Proceedings of the 19th Design Automation Conference, 1982

1981

Data Compression of the Kanji Character Patterns Digitized on the Hexagonal Mesh.

IEEE Trans. Pattern Anal. Mach. Intell., 1981

Dynamic Clustering Procedures for Bibliographic Data.

Proceedings of the Theoretical Issues in Information Retrieval, Proceedings of the Fourth International Conference on Information Storage and Retrieval, Oakland, California, USA, May 31, 1981

Data compression procedures utilizing the similarity of data.

Proceedings of the American Federation of Information Processing Societies: 1981 National Computer Conference, 1981

1979

Organization of quasi-consecutive retrieval files.

Inf. Syst., 1979

Use of abstracted characteristics of data in relational databases.

Proceedings of the IEEE Computer Society's Third International Computer Software and Applications Conference, 1979

Semantic aspects of data dependencies and their application to relational database design.

Proceedings of the IEEE Computer Society's Third International Computer Software and Applications Conference, 1979

Hierarchical string pattern matching using dynamic pattern matching machines.

Proceedings of the IEEE Computer Society's Third International Computer Software and Applications Conference, 1979

1978

A Linear Storage Space Algorithm for a Reference Structure Index.

Inf. Process. Lett., 1978

A file organization suitable for relational database operations.

Proceedings of the Mathematical Studies of Information Processing, 1978

Problems of Relational Database Design.

Proceedings of the Data Base Design Techniques I: Requirements and Logical Structures, 1978

1977

Labolink: An Optically Linked Laboratory Computer Network.

IEEE Computer, 1977

A Relational Data Language with Simplified Binary Relation Handling Capability.

Proceedings of the Third International Conference on Very Large Data Bases, 1977

1974

Power Minimization Problems of Logic Networks.

IEEE Trans. Computers, 1974

1972

Controllability of Seqential Machines

Information and Control, November, 1972

Finite Memory Machines Satisfying the Lower Bound of Memory

Information and Control, March, 1972

1971

The Upper Bound of K in K-Lossless Sequential Machines

Information and Control, December, 1971

1970

Two-State Two-Symbol Probabilistic Automata

Information and Control, May, 1970

On Finite-Memory Sequential Machines.

IEEE Trans. Computers, 1970

1969

Some Algebraic Properties of Sets of Stochastic Matrices

Information and Control, April, 1969

1968

On Autonomous Logic Nets of Threshold Elements.

IEEE Trans. Computers, 1968

Realization of Arbitrary Logic Functions by Completely Monotonic Functions and Its Applications to Threshold Logic.

IEEE Trans. Computers, 1968

A Theory of Completely Monotonic Functions and its Applications to Threshold Logic.

IEEE Trans. Computers, 1968

1965

A Lower Bound of the Number of Threshold Functions.

IEEE Trans. Electronic Computers, 1965