Nagisa Ishiura

According to our database, Nagisa Ishiura authored at least 34 papers between 1987 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Full Hardware Implementation of FreeRTOS-Based Real-Time Systems.

Wakako Nakano, Yukino Shinohara, Nagisa Ishiura

Proceedings of the IEEE Region 10 Conference, 2021

2018

Extending equivalence transformation based program generator for random testing of C compilers.

Shogo Takakura, Mitsuyoshi Iwatsuji, Nagisa Ishiura

Proceedings of the 9th ACM SIGSOFT International Workshop on Automating TEST Case Design, 2018

Random testing of compilers' performance based on mixed static and dynamic code comparison.

Kota Kitaura, Nagisa Ishiura

Proceedings of the 9th ACM SIGSOFT International Workshop on Automating TEST Case Design, 2018

Synthesis of Full Hardware Implementation of RTOS-Based Systems.

Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara

Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

2017

CF3: Test Suite for Arithmetic Optimization of C Compilers.

Yusuke Hibino, Hirofumi Ikeo, Nagisa Ishiura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Speculative execution in distributed controllers for high-level synthesis.

Miho Shimizu, Nagisa Ishiura, Sayuri Ota, Wakako Nakano

Proceedings of the International Symposium on Rapid System Prototyping, 2017

Binary synthesis implementing external interrupt handler as independent module.

Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama

Proceedings of the International Symposium on Rapid System Prototyping, 2017

Distributed memory architecture for high-level synthesis of embedded controllers from Erlang.

Kagumi Azuma, Nagisa Ishiura, Nobuaki Yoshida, Hiroyuki Kanbara

Proceedings of the 16th ACM SIGPLAN International Workshop on Erlang, 2017

2016

Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs.

Atsushi Hashimoto, Nagisa Ishiura

IPSJ Trans. Syst. LSI Des. Methodol., 2016

Reverse Engineering from Mainframe Assembly to C Codes in Legacy Migration.

Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai, Ryo Aoki, Takashi Ogawara

Proceedings of the 5th IIAI International Congress on Advanced Applied Informatics, 2016

Random testing of C compilers based on test program generation by equivalence transformation.

Kazuhiro Nakamura, Nagisa Ishiura

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014

Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions.

Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura

IPSJ Trans. Syst. LSI Des. Methodol., 2014

2010

Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors.

Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).

Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura

IPSJ Trans. Syst. LSI Des. Methodol., 2010

2008

High-Level Synthesis of Software Function Calls.

Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Special Section on VLSI Design and CAD Algorithms.

Nagisa Ishiura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2002

Datapath oriented codesign method of application specific DSPs using retargetable compiler.

Nagisa Ishiura, Tatsuo Watanabe

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000

Thread partitioning method for hardware compiler bach.

Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe

Proceedings of ASP-DAC 2000, 2000

1998

Binding and Scheduling Algorithms for Highly Retargetable Compilation.

Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe

Proceedings of the ASP-DAC '98, 1998

1995

Optimal Scheduling for Conditional Recource Sharing.

Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Fault simulation for multiple faults by Boolean function manipulation.

Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992

Linear time fault simulation algorithm using a content addressable memory.

Nagisa Ishiura, Shuzo Yajima

Proceedings of the conference on European design automation, 1992

1991

Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets.

Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Minimazation of Binary Decision Diagrams Based on Exchanges of Variables.

Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing.

Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima

Proceedings of the 28th Design Automation Conference, 1991

Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits.

Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima

Proceedings of the 28th Design Automation Conference, 1991

1990

Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor.

Nagisa Ishiura, Masayuki Ito, Shuzo Yajima

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Formal semantics of UDL/I and its applications to CAD/DA tools.

Hiroto Yasuura, Nagisa Ishiura

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation.

Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram.

Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Semantics of a Hardware Design Language for Japanese Standardization.

Hiroto Yasuura, Nagisa Ishiura

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits.

Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987

High-Speed Logic Simulation on Vector Processors.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987