Shinji Kimura

According to our database, Shinji Kimura authored at least 103 papers between 1982 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Input Data Format for Sparse Matrix in Quantum Annealing Emulator.

Sohei Shimomai, Kei Ueda, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

2023

Theory and Application of Topology-Based Exact Synthesis for Majority-Inverter Graphs.

Xianliang Ge, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., September, 2023

Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier.

Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura

IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks.

Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

An 8-point Approximate DCT Design with Optimized Signed Digit Encoding.

Zekun Wang, Shinichi Nishizawa, Shinji Kimura

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction.

Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery.

Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Compressed Input Data Format of Quantum Annealing Emulator.

Sohei Shimomai, Kei Ueda, Shinji Kimura

Proceedings of the Data Compression Conference, 2023

2022

Exploration of an Inflection Point of Ventilation Parameters with Anaerobic Threshold Using Strucchange.

Takenori Aida, Akira Shionoya, Hirofumi Nonaka, Kouji Hayami, Hisashi Uchiyama, Masahiro Nagamori, Satoshi Ohhashi, Mai Kobayashi, Tsugumi Takayama, Shinji Kimura

Sensors, 2022

ApproxTorch: An Approximate Multiplier Evaluation Environment for CNNs based on Pytorch.

Ke Ma, Shinji Kimura

Proceedings of the 19th International SoC Design Conference, 2022

Topology-Based Exact Synthesis for Majority Inverter Graph.

Xianliang Ge, Shinji Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding.

Rongyu Ding, Yi Guo, Heming Sun, Shinji Kimura

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules.

Yi Guo, Heming Sun, Ping Lei, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Accuracy-Configurable Low-Power Approximate Floating-Point Multiplier Based on Mantissa Bit Segmentation.

Jie Li, Yi Guo, Shinji Kimura

Proceedings of the 2020 IEEE Region 10 Conference, 2020

Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules.

Yi Guo, Heming Sun, Shinji Kimura

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme.

Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Design of Low-Cost Approximate Multipliers Based on Probability-Driven Inexact Compressors.

Yi Guo, Heming Sun, Ping Lei, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors.

Yi Guo, Heming Sun, Shinji Kimura

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Approximate Multiplier Using Reordered 4-2 Compressor with OR-based Error Compensation.

Yufeng Xu, Yi Guo, Shinji Kimura

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC.

Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto

IEEE Trans. Circuits Syst. Video Technol., 2018

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging.

Aya Ibrahim, Shuping Zhang, Federico Angiolini, Marcel Arditi, Shinji Kimura, Satoshi Goto, Jean-Philippe Thiran, Giovanni De Micheli

IEEE Trans. Biomed. Circuits Syst., 2018

Lossy Compression for Embedded Computer Vision Systems.

Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura, Satoshi Goto

IEEE Access, 2018

Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering.

Zhenhao Liu, Yi Guo, Xiaoting Sun, Shinji Kimura

Proceedings of the TENCON 2018, 2018

Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier.

Yi Guo, Heming Sun, Shinji Kimura

Proceedings of the TENCON 2018, 2018

Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression.

Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Embedded Frame Compression for Energy-Efficient Computer Vision Systems.

Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing.

Xiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA.

Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity.

Canran Jin, Heming Sun, Shinji Kimura

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors.

Yi Guo, Heming Sun, Li Guo, Shinji Kimura

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC.

Heming Sun, Dajiang Zhou, Landan Hu, Shinji Kimura, Satoshi Goto

IEEE Trans. Multim., 2017

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.

Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

IEEE J. Solid State Circuits, 2017

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor.

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto

IEICE Trans. Electron., 2017

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System.

Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Accelerating HEVC Inter Prediction with Improved Merge Mode Handling.

Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering.

Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Effective write-reduction method for MLC non-volatile memory.

Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A low-cost approximate 32-point transform architecture.

Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform.

Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Power-efficient and slew-aware three dimensional gated clock tree synthesis.

Minghao Lin, Heming Sun, Shinji Kimura

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.

Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems.

Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Proceedings of the 2016 IEEE International Conference on Multimedia & Expo Workshops, 2016

CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks.

Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Optimization of area and power in multi-mode power gating scheme for static memory elements.

Xing Su, Shinji Kimura

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Low-Power Motion Estimation Processor with 3D Stacked Memory.

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory.

Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Merge mode based fast inter prediction for HEVC.

Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura

Proceedings of the 2015 Visual Communications and Image Processing, 2015

An independent bandwidth reduction device for HEVC VLSI video system.

Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder.

Landan Hu, Heming Sun, Dajiang Zhou, Shinji Kimura

Proceedings of the 2015 IEEE International Conference on Multimedia & Expo Workshops, 2015

A bit-write reduction method based on error-correcting codes for non-volatile memories.

Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding.

Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder.

Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto

Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Fast SAO estimation algorithm and its VLSI architecture.

Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

2013

Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis.

Naoya Okada, Yuichi Nakamura, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An Exact Approach for GPC-Based Compressor Tree Synthesis.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization.

Yu Jin, Zhe Du, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Eyeglass-based hands-free videophone.

Shinji Kimura, Masaaki Fukumoto, Tsutomu Horikoshi

Proceedings of the 17th Annual International Symposium on Wearable Computers. ISWC 2013, 2013

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors.

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Controlling-value-based power gating considering controllability propagation and power-off probability.

Zhe Du, Yu Jin, Shinji Kimura

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation.

Xin Man, Takashi Horiyama, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating.

Yu Jin, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011

Multi-Operand Adder Synthesis Targeting FPGAs.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Multi-stage power gating based on controlling values of logic gates.

Yu Jin, Shinji Kimura

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

High-parallel LDPC decoder with power gating design.

Ying Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating.

Xin Man, Takashi Horiyama, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Multi-operand adder synthesis on FPGAs using generalized parallel counters.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Framework for Parallel Prefix Adder Synthesis Considering Switching Activities.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping.

Chengjie Zang, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Foreword.

Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity.

Lei Chen, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An objective and subjective evaluation of an autostereoscopic 3d display.

Masashi Tsuboi, Shinji Kimura, Tsutomu Horikoshi

Proceedings of the 27th International Conference on Human Factors in Computing Systems, 2009

2008

Issue Mechanism for Embedded Simultaneous Multithreading Processor.

Chengjie Zang, Shigeki Imai, Steven Frank, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration.

Yun Yang, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array.

Yun Yang, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements.

Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Synthesis of parallel prefix adders considering switching activities.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Proceedings of the 26th International Conference on Computer Design, 2008

2006

Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification.

Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains.

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique.

Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Transition-based coverage estimation for symbolic model checking.

Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Special Section on VLSI Design and CAD Algorithms.

Shinji Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Extended abstract: transition traversal coverage estimation for symbolic model checking.

Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection.

Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Low Power Test Compression Technique for Designs with Multiple Scan Chain.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.

Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Minimization of fractional wordlength on fixed-point conversion for high-level synthesis.

Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation.

Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis.

Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

Look Up Table Compaction Based on Folding of Logic Functions.

Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Folding of logic functions and its application to look up table compaction.

Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

Speech recognition chip for monosyllables.

Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe

Proceedings of ASP-DAC 2001, 2001

A real-time 64-monosyllable recognition LSI with learning mechanism.

Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe

Proceedings of ASP-DAC 2001, 2001

2000

Multi-clock path analysis using propositional satisfiability.

Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe

Proceedings of ASP-DAC 2000, 2000

An application specific Java processor with reconfigurabilities.

Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe

Proceedings of ASP-DAC 2000, 2000

1998

Waiting false path analysis of sequential logic circuits for performance optimization.

Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.

Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1995

Residue BDD and Its Application to the Verification of Arithmetic Circuits.

Shinji Kimura

Proceedings of the 32st Conference on Design Automation, 1995

1992

Precise timing verification of logic circuits under combined delay model.

Shinji Kimura, Shigemi Kashima, Hiromasa Haneda

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1990

A parallel algorithm for constructing binary decision diagrams.

Shinji Kimura, Edmund M. Clarke

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1987

Description and verification of input constraints and input-output specifications of logic circuits.

Shinji Kimura, Shuzo Yajima

Syst. Comput. Jpn., 1987

1982

An Interactive Simulation System for structured logic design - ISS.

Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima

Proceedings of the 19th Design Automation Conference, 1982