Hiroyuki Ochi
Orcid: 0000-0002-9075-6711
According to our database1,
Hiroyuki Ochi
authored at least 72 papers
between 1991 and 2023.
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Bibliography
2023
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations.
IEICE Trans. Electron., October, 2023
IPSJ Trans. Syst. LSI Des. Methodol., 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022
2021
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021
2020
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Embed. Syst. Lett., 2018
2017
Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
2016
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs.
IEICE Trans. Electron., 2015
A -0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015
Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element.
IEICE Trans. Electron., 2013
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis.
IEICE Trans. Electron., 2013
Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array.
Proceedings of the Design, Automation and Test in Europe, 2013
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
ACM Trans. Embed. Comput. Syst., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
IPSJ Trans. Syst. LSI Des. Methodol., 2009
Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009
Hot-Swapping architecture extension for mitigation of permanent functional unit faults.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
An architecture of photo core transform in HD photo coding system for embedded systems of various bandwidths.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
J. Circuits Syst. Comput., 2007
A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007
2006
A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups.
IEICE Trans. Inf. Syst., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Pedestrian Recognition in Far-Infrared Images by Combining Boosting-Based Detection and Skeleton-Based Stochastic Tracking.
Proceedings of the Advances in Image and Video Technology, First Pacific Rim Symposium, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
2005
An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A Localization Scheme for Sensor Networks based onWireless Communication with Anchor Groups.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005
2003
Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2000
Proceedings of ASP-DAC 2000, 2000
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1991
Proceedings of the 28th Design Automation Conference, 1991
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991