Paul Scheffler

Orcid: 0000-0003-4230-1381

According to our database1, Paul Scheffler authored at least 9 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
A High-Performance, Energy-Efficient Modular DMA Engine Architecture.
IEEE Trans. Computers, January, 2024

2023
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra.
IEEE Trans. Parallel Distributed Syst., December, 2023

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV.
CoRR, 2023

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
Banshee: A Fast LLVM-Based RISC-V Binary Translator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Artificial Intelligence in Purchasing: Facilitating Mechanism Design-based Negotiations.
Appl. Artif. Intell., 2020


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