Somayeh Sardashti

According to our database1, Somayeh Sardashti authored at least 12 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2018
F1 Query: Declarative Querying at Scale.
Proc. VLDB Endow., 2018

2017
Could Compression Be of General Use? Evaluating Memory Compression across Domains.
ACM Trans. Archit. Code Optim., 2017

2016
Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache.
ACM Trans. Archit. Code Optim., 2016

2015
A Primer on Compression in the Memory Hierarchy
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01751-3, 2015

2014
Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization.
IEEE Micro, 2014

Skewed Compressed Caches.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique.
Proceedings of the International Conference on Supercomputing, 2012

2011
The gem5 simulator.
SIGARCH Comput. Archit. News, 2011

2008
High Performance Mathematical Quarter-Pixel Motion Estimation with Novel Rate Distortion Metric for H.264/AVC.
Proceedings of the Advances in Computer Science and Engineering, 2008

2006
Muli-Issue Multi-Threaded Stream Processor.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

2004
Thread-Sensitive Instruction Issue for SMT Processors.
IEEE Comput. Archit. Lett., 2004


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