According to our database1, Korey Sewell authored at least 7 papers between 2011 and 2013.
Legend:Book In proceedings Article PhD thesis Other
Limits of Parallelism and Boosting in Dim Silicon.
IEEE Micro, 2013
Scaling towards kilo-core processors with asymmetric high-radix topologies.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Swizzle-Switch Networks for Many-Core Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Assessing the performance limits of parallelized near-threshold computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
The gem5 simulator.
SIGARCH Computer Architecture News, 2011