Joel Hestness

Orcid: 0000-0001-6920-0906

According to our database1, Joel Hestness authored at least 24 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
MediSwift: Efficient Sparse Pre-trained Biomedical Language Models.
CoRR, 2024

2023
Position Interpolation Improves ALiBi Extrapolation.
CoRR, 2023

BTLM-3B-8K: 7B Parameter Performance in a 3B Parameter Model.
CoRR, 2023

SlimPajama-DC: Understanding Data Combinations for LLM Training.
CoRR, 2023

Cerebras-GPT: Open Compute-Optimal Language Models Trained on the Cerebras Wafer-Scale Cluster.
CoRR, 2023

2022
RevBiFPN: The Fully Reversible Bidirectional Feature Pyramid Network.
CoRR, 2022

Time Dependency, Data Flow, and Competitive Advantage.
CoRR, 2022

Time and the Value of Data.
CoRR, 2022

Efficiently Disentangle Causal Representations.
CoRR, 2022

2021
Pipelined Backpropagation at Scale: Training Large Models without Batches.
Proceedings of Machine Learning and Systems 2021, 2021

2020
Memory Efficient 3D U-Net with Reversible Mobile Inverted Bottlenecks for Brain Tumor Segmentation.
Proceedings of the Brainlesion: Glioma, Multiple Sclerosis, Stroke and Traumatic Brain Injuries, 2020

2019
A survey of 25 years of evaluation.
Nat. Lang. Eng., 2019

Beyond human-level accuracy: computational challenges in deep learning.
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019

Compositional Generalization for Primitive Substitutions.
Proceedings of the 2019 Conference on Empirical Methods in Natural Language Processing and the 9th International Joint Conference on Natural Language Processing, 2019

2017
Deep Learning Scaling is Predictable, Empirically.
CoRR, 2017

Convolutional Recurrent Neural Networks for Small-Footprint Keyword Spotting.
Proceedings of the Interspeech 2017, 2017

2015
gem5-gpu: A Heterogeneous CPU-GPU Simulator.
IEEE Comput. Archit. Lett., 2015

GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

2014
A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2012
A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips.
IEEE Micro, 2012

2011
The gem5 simulator.
SIGARCH Comput. Archit. News, 2011

Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
Netrace: dependency-driven trace-based network-on-chip simulation.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

2009
Express Cube Topologies for on-Chip Interconnects.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009


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