Souradip Sarkar

According to our database, Souradip Sarkar authored at least 10 papers between 2007 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A Reconfigurable Architecture for Posit Arithmetic.

Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

Small Transactions with Sustainable Incentives.

Fabio Pianese, Matteo Signorini, Souradip Sarkar

Proceedings of the 9th IFIP International Conference on New Technologies, 2018

Quater-imaginary base for complex number arithmetic circuits.

Souradip Sarkar, Manil Dev Gomony

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2012

NoC-Based Hardware Accelerator for Breakpoint Phylogeny.

Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman

IEEE Trans. Computers, 2012

Power-aware multi-core simulation for early design stage hardware/software co-optimization.

Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era.

Wim Heirman, Trevor E. Carlson, Souradip Sarkar, Pieter Ghysels, Wim Vanroose, Lieven Eeckhout

Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

2010

Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.

Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman

IEEE Trans. Computers, 2010

Hardware accelerators for biocomputing: A survey.

Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem.

Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2007

Multiple clock domain synchronization for network on chip architectures.

Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande

Proceedings of the 2007 IEEE International SOC Conference, 2007