Sourajeet Roy

According to our database, Sourajeet Roy authored at least 14 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Metalearning Based Adaptive Compact Modeling Framework for Advanced Transistors Across Technology Nodes.

Srishti Parandiyal, Abhishek Kumar, M. Ehteshamuddin, Anamika Singh, Kumar Sheelvardhan, Samrat Ray, Abhishek Somani, Sourajeet Roy, Avirup Dasgupta

IEEE Trans. Artif. Intell., October, 2025

Scientific machine learning for generic compact model parameter extraction of nanoscale transistors.

Kumar Sheelvardhan, Surila Guglani, Abhilash Dubey, Shashank Dubey, Sindhu Ramaswamy, Vaidy Subramanian, Kassandra Anderson, Glenn Workman, Sourajeet Roy, Avirup Dasgupta

Eng. Appl. Artif. Intell., 2025

Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM Architectures.

Anubha Sehgal, Sandeep Soni, Sumit Diware, Alok Kumar Shukla, Sourajeet Roy, Rajendra Bishnoi

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Enhancing Parallelism and Energy-Efficiency in SOT-MRAM based CIM Architecture for On-Chip Learning.

Anubha Sehgal, Alok Kumar Shukla, Sumit Diware, Sandeep Soni, Seema Dhull, Sonal Shreya, Sourajeet Roy, Rajendra Bishnoi

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2023

Fast Multi-ANN Composite Models for Repeater Optimization in Presence of Parametric Uncertainty for on-Chip Hybrid Copper-Graphene Interconnects.

Suyash Kushwaha, Avirup Dasgupta, Sourajeet Roy, Rohit Sharma

IEEE Access, 2023

2022

A Bilevel Multi-Fidelity Polynomial Chaos Approach for the Uncertainty Quantification of MWCNT Interconnect Networks With Variable Imperfect Contact Resistances.

Surila Guglani, K. M. Dimple, Sourajeet Roy, Rohit Sharma, Brajesh Kumar Kaushik

IEEE Access, 2022

Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.

Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs.

Surila Guglani, Avirup Dasgupta, Ming-Yen Kao, Chenming Hu, Sourajeet Roy

Proceedings of the Device Research Conference, 2022

2020

Statistical Analysis of Temperature Variability on the Write Efficiency of Spin-Orbit Torque MRAM using Polynomial Chaos Metamodels.

Sonal Shreya, Surila Guglani, Brajesh Kumar Kaushik, Sourajeet Roy

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2017

A Holistic Approach to Transforming Undergraduate Electrical Engineering Education.

Anthony A. Maciejewski, Thomas W. Chen, Zinta S. Byrne, Michael A. De Miranda, Laura B. Sample Mcmeeking, Branislav M. Notaros, Ali Pezeshki, Sourajeet Roy, Andrea M. Leland, Melissa D. Reese, Alma H. Rosales, Thomas J. Siller, Richard F. Toftness, Olivera Notaros

IEEE Access, 2017

2016

Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits.

Majid Ahadi, Sourajeet Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2011

Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations.

Sourajeet Roy, Anestis Dounavis

IEEE Trans. Very Large Scale Integr. Syst., 2011

Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution.

Sourajeet Roy, Anestis Dounavis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009

Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation.

Sourajeet Roy, Anestis Dounavis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009