Spencer Leuenberger

According to our database1, Spencer Leuenberger authored at least 18 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Charge-Domain Switched-G<sub>m</sub>-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier.
IEEE J. Solid State Circuits, 2019

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Power Optimized Comparator Selecting Method For Stochastic ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Power Efficient SAR Algorithm for High Resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 0.6mW 31MHz 4<sup>th</sup>-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A single OpAmp 2<sup>nd</sup>-Order ΔΣ ADC with a double integrating quantizer.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Analysis and performance trade-offs of linearity calibration for stochastic ADCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Resistive correction of low output impedance high-speed current-steering DACs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014


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