Koichi Hamashita
According to our database1,
Koichi Hamashita
authored at least 34 papers
between 2005 and 2021.
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Bibliography
2021
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 951-fs<sub>rms</sub> Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.
IEEE J. Solid State Circuits, 2020
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier.
IEEE J. Solid State Circuits, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
IEEE J. Solid State Circuits, 2014
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier.
Proceedings of the Symposium on VLSI Circuits, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
Direct-digital modulation (DIDIMO) transmitter with -156dBc/Hz Rx-band noise using FIR structure.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE J. Solid State Circuits, 2011
Binary Access Memory: An optimized lookup table for successive approximation applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators.
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback.
IEEE J. Solid State Circuits, 2009
A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver.
IEEE J. Solid State Circuits, 2009
A Fifth-Order G<sub>m</sub>-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR.
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2005
IEEE J. Solid State Circuits, 2005