Hyuk Sun

Orcid: 0000-0001-5838-0075

According to our database1, Hyuk Sun authored at least 11 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
A 951-fs<sub>rms</sub> Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.
IEEE J. Solid State Circuits, 2020

2018
An Oversampling Stochastic ADC Using VCO-Based Quantizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

MDLL/PLL dual-path clock generator.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A VCO-based spatial averaging stochastic ADC.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
A 10-Bit 800-MHz 19-mW CMOS ADC.
IEEE J. Solid State Circuits, 2014


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