Kazuki Sobue

According to our database1, Kazuki Sobue authored at least 16 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 951-fs<sub>rms</sub> Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.
IEEE J. Solid State Circuits, 2020

A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier.
IEEE J. Solid State Circuits, 2019

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
An Oversampling Stochastic ADC Using VCO-Based Quantizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
Parallel gain enhancement technique for switched-capacitor circuits.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Ring Amplifiers for Switched Capacitor Circuits.
IEEE J. Solid State Circuits, 2012

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers.
Proceedings of the Symposium on VLSI Circuits, 2012


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