Yang Xu

Affiliations:
  • Texas Instruments, Dallas, TX, USA (since 2017)
  • Oregon State University, School of Electrical Engineering and Computer Science, Corvallis, OR, USA (2013 - 2017)
  • Tsinghua University, Institute of Microelectronics, Beijing, China (2010 - 2013)


According to our database1, Yang Xu authored at least 25 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2020
A Charge-Domain Switched-G<sub>m</sub>-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter.
IEEE J. Solid State Circuits, 2020

2019
An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 0.1-5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS.
Microelectron. J., 2018

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A highly compact wideband continuous-time transimpedance low-pass filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Voltage domain correction technique for timing skew errors in time interleaved ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.65mW 20MHz 5<sup>th</sup>-order low-pass filter with +28.8dBm IIP3 using source follower coupling.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 0.6mW 31MHz 4<sup>th</sup>-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1/2/4MHz multi-mode reconfigurable lowpass/complex bandpass CT ΣΔ modulator for short range wireless receiver.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Inherently linear time symmetric pulse width modulation.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 0.1-5GHz flexible SDR receiver in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations.
Proceedings of the ESSCIRC 2013, 2013

An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A hybrid approach to I/Q imbalance self-calibration in reconfigurable low-IF receivers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Power-scalable multi-mode reconfigurable continuous-time lowpass/quadrature bandpass sigma-delta modulator for zero/low-IF receivers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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