Huseyin Ekin Sumbul

According to our database, Huseyin Ekin Sumbul authored at least 25 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications.

Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné

IEEE Micro, 2024

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.

Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries.

Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné

Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

2022

DRESS: Dynamic REal-time Sparse Subnets.

Zhongnan Qu, Syed Shakib Sarwar, Xin Dong, Yuecheng Li, Huseyin Ekin Sumbul, Barbara De Salvo

CoRR, 2022

Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks.

Dominika Przewlocka-Rus, Syed Shakib Sarwar, Huseyin Ekin Sumbul, Yuecheng Li, Barbara De Salvo

CoRR, 2022

Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications.

Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows.

Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars.

Huseyin Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS.

Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy

IEEE J. Solid State Circuits, 2021

2020

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS.

Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.

Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.

Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.

Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.

Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS.

Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy

IEEE J. Solid State Circuits, 2019

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.

Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.

Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS.

Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2015

A Novel Design Methodology for Synthesizing Application-Specific Logic-in-Memory Blocks.

Huseyin Ekin Sumbul

PhD thesis, 2015

A synthesis methodology for application-specific logic-in-memory designs.

Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Efficient and secure intellectual property (IP) design with split fabrication.

Kaushik Vaidyanathan, Renzhi Liu, Huseyin Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Building trusted ICs using split fabrication.

Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware.

Qiuling Zhu, Tobias Graf, Huseyin Ekin Sumbul, Larry T. Pileggi, Franz Franchetti

Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing.

Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2010

Fast Smith-Waterman hardware implementation.

Zubair Nawaz, Koen Bertels, Huseyin Ekin Sumbul

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010