Lavanya Subramanian
Orcid: 0000-0001-9809-3361
According to our database1,
Lavanya Subramanian
authored at least 28 papers
between 2011 and 2023.
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Bibliography
2023
FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity.
ACM Trans. Embed. Comput. Syst., March, 2023
2022
FARSI: Facebook AR System Investigator for Agile Domain-Specific System-on-Chip Exploration.
CoRR, 2022
2020
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019
2018
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems.
CoRR, 2018
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems.
CoRR, 2018
Proceedings of the International Symposium on Memory Systems, 2018
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
Proc. ACM Meas. Anal. Comput. Syst., 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators.
ACM Trans. Archit. Code Optim., 2016
Social Networking Sites: College Students' Patterns of Use and Concerns for Privacy and Trust by Gender, Ethnicity, and Employment Status.
Int. J. Inf. Commun. Technol. Educ., 2016
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
CoRR, 2016
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism.
CoRR, 2016
2015
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators.
CoRR, 2015
CoRR, 2015
Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management.
CoRR, 2015
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2015
The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015
2014
Supercomput. Front. Innov., 2014
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
MISE: Providing performance predictability and improving fairness in shared main memory systems.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
2011
Reducing memory interference in multicore systems via application-aware memory channel partitioning.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011