Stephen A. Szygenda

According to our database, Stephen A. Szygenda authored at least 47 papers between 1970 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

System Probability Distribution Modeling Using MDDs.

Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2008

A Systems Engineering Approach for Identifying the Most Critical Links of a Highway System: A Framework Consisting of a Methodology and Mathematical Model.

Gerard Ibarra, Jerrell T. Stracener, Stephen A. Szygenda

IEEE Syst. J., 2008

Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility.

Chad M. Lawler, Michael A. Harper, Stephen A. Szygenda, Mitchell A. Thornton

Int. J. Bus. Inf. Syst., 2008

2004

A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking.

Lun Li, Mitchell A. Thornton, Stephen A. Szygenda

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Test vector generation and classification using FSM traversals.

Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem.

Sungho Kang, Stephen A. Szygenda

Simul., 2003

1997

Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects.

Charles Wiley, A. T. Campbell III, Stephen A. Szygenda, Donald S. Fussell, Fred Hudson

Proceedings of the Graphics Interface 1997 Conference, 1997

Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation.

Saghir A. Shaikh, Stephen A. Szygenda

Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997

Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System.

Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, D. Kacprzak, Stephen A. Szygenda

Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997

1996

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture.

Sungho Kang, Youngmin Hur, Stephen A. Szygenda

VLSI Design, 1996

An Integrated Hardware Array for Very High Speed Logic Simulation.

E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott

VLSI Design, 1996

CON²FERS: A Concurrent Concurrent Fault and Design Error Simulator.

Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

A Graphical Simulation and Automatic Model Generation System.

Youngmin Hur, Stephen A. Szygenda

Proceedings of the Modelling and Simulation, 1996

A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling.

Youngmin Hur, Stephen A. Szygenda

Proceedings of the Proceedings 29st Annual Simulation Symposium (SS '96), 1996

1995

Statistics on concurrent fault and design error simulation.

Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation.

Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

Special purpose array processor for digital logic simulation.

Youngmin Hur, Stephen A. Szygenda

Proceedings of the Proceedings 28st Annual Simulation Symposium (SS '95), 1995

1994

The simulation automation system (SAS); concepts, implementation, and results.

Sungho Kang, Stephen A. Szygenda

IEEE Trans. Very Large Scale Integr. Syst., 1994

Automatic Simulator Generation System.

Sungho Kang, Stephen A. Szygenda

Simul., 1994

Automatic Functional Model Generation for Parallel Fault and Design Error Simulations.

Shuchih Ernest Chang, Stephen A. Szygenda

Int. J. Artif. Intell. Tools, 1994

Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling.

Sungho Kang, Stephen A. Szygenda

IEEE Des. Test Comput., 1994

1993

m3D: A Multidimensional Dynamic Configurable Router.

Charles Wiley, K. M. Lau, Stephen A. Szygenda

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Automatic VHDL Model Generation System.

Sungho Kang, Stephen A. Szygenda

Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992

Modeling and Simulation of Design Errors.

Sungho Kang, Stephen A. Szygenda

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

New design error modeling and metrics for design validation.

Sungho Kang, Stephen A. Szygenda

Proceedings of the conference on European design automation, 1992

The automatic element routine generator: an automatic programming tool for functional simulator design.

Cheng-I Chuang, Stephen A. Szygenda, James D. Baker

Proceedings of the Proceedings 25th Annual Simulation Symposium (ANSS-25 1992), 1992

1990

MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach.

Jin-Hyeung Kong, Stephen A. Szygenda

Comput. Aided Des., 1990

1988

SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests.

Asad Karim, Stephen A. Szygenda

Proceedings of the First International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1988, June 1-3, 1988, Tullahoma, TN, USA. ACM, 1988, 1988

1987

Technology transfer: commercializing university research.

Stephen A. Szygenda, M. Wilson

Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow, 1987

1977

Detection of static and dynamic hazards in logic nets.

Ajoy K. Bose, Stephen A. Szygenda

Proceedings of the 14th Design Automation Conference, 1977

Design of a diagnosable and fault-tolerant input/output controller.

Ajoy K. Bose, Stephen A. Szygenda

Proceedings of the American Federation of Information Processing Societies: 1977 National Computer Conference, 1977

1976

Modeling and Digital Simulation for Design Verification and Diagnosis.

Stephen A. Szygenda, Edward W. Thompson

IEEE Trans. Computers, 1976

A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems.

N. Billawala, Stephen A. Szygenda, Ewald W. Thomson

Proceedings of the 2nd International Conference on Software Engineering, 1976

1975

Digital Logic Simulation in a Time-Based, Table-Driven Environment.

Edward W. Thompson, Stephen A. Szygenda

Computer, 1975

Digital Systems Simulation.

Stephen A. Szygenda

Computer, 1975

Three levels of accuracy for the simulation of different fault types in digital systems.

Edward W. Thompson, Stephen A. Szygenda

Proceedings of the 12th Design Automation Conference, 1975

1974

Implemented techniques for handling spikes in an assignable delay simulator.

Stephen A. Szygenda, Anthony A. Lekkos, John L. Fike

Proceedings of the 7th conference on Winter simulation, 1974

Timing analysis for digital fault simulation using assignable delays.

Edward W. Thompson, Stephen A. Szygenda, N. Billawala, R. Pierce

Proceedings of the 11th Design Automation Workshop, 1974

1973

Deriving Design Guidelines for Diagnosable Computer Systems.

John M. Hemphill, Stephen A. Szygenda

Proceedings of the 1st Annual Symposium on Computer Architecture, 1973

Integrated techniques for functional and gate-level digital logic simulation.

Stephen A. Szygenda, Anthony A. Lekkos

Proceedings of the 10th Design Automation Workshop, 1973

Techniques and modules for element specification in a time - delay logic simulator.

John L. Fike, Stephen A. Szygenda

Proceedings of the 1st Symposium on Simulation of Computer Systems, 1973

1972

TEGAS2 - anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic.

Stephen A. Szygenda

Proceedings of the 9th Design Automation Workshop, 1972

Fault insertion techniques and models for digital logic simulation.

Stephen A. Szygenda, Edward W. Thompson

Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '72 Fall Joint Computer Conference, December 5-7, 1972, Anaheim, California, USA, 1972

Modular requirements for digital logic simulation at a predefined functional level.

Cliff W. Hemming Jr., Stephen A. Szygenda

Proceedings of the ACM annual conference, 1972

1971

Time flow mechanisms for use in digital logic simulation.

Stephen A. Szygenda, Cliff W. Hemming Jr., John M. Hemphill

Proceedings of the 5th conference on Winter simulation, 1971

Coding techniques for failure recovery in a distributive modular memory organization.

Stephen A. Szygenda, Michael J. Flynn

Proceedings of the American Federation of Information Processing Societies: AFIPS Conference Proceedings: 1971 Spring Joint Computer Conference, 1971

1970

A model and implementation of a universal time delay simulator for large digital nets.

Stephen A. Szygenda, David M. Rouse, Edward W. Thompson

Proceedings of the American Federation of Information Processing Societies: AFIPS Conference Proceedings: 1970 Spring Joint Computer Conference, 1970