Theodore W. Manikas

According to our database, Theodore W. Manikas authored at least 31 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift.

Hui Jiang, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas

J. Electron. Test., April, 2023

CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques.

Andrew Havard, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton

CoRR, 2023

Harvesting Wasted Clock Cycles for Efficient Online Testing.

Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal

Proceedings of the IEEE European Test Symposium, 2023

2021

3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.

Soha Alhelaly, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Ping Gui, Alfred L. Crouch

IEEE Trans. Emerg. Top. Comput., 2021

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.

Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar

Proceedings of the IEEE International Test Conference, 2021

Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus.

Aviraj Sinha, Michael A. Taylor, Nathan Srirama, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton

Proceedings of the IEEE Conference on Control Technology and Applications, 2021

2019

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.

Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar

J. Electron. Test., 2019

Test Architecture for Fine Grained Capture Power Reduction.

Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2017

Automated Markov-chain based analysis for large state spaces.

Kaitlin N. Smith, Michael A. Taylor, Anna A. Carroll, Theodore W. Manikas, Mitchell A. Thornton

Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

Detecting a trojan die in 3D stacked integrated circuits.

Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Kundan Nepal, Alfred L. Crouch

Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

2016

Reliability block diagram extensions for non-parametric probabilistic analysis.

Philip C. Davis, Mitchell A. Thornton, Theodore W. Manikas

Proceedings of the Annual IEEE Systems Conference, 2016

Using Existing Reconfigurable Logic in 3D Die Stacks for Test.

Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter

Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

2015

Repairing a 3-D Die-Stack Using Available Programmable Logic.

Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams.

Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein

J. Multiple Valued Log. Soft Comput., 2015

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas

IEICE Trans. Inf. Syst., 2014

System Probability Distribution Modeling Using MDDs.

Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2013

Spectral Response of Ternary Logic Netlists.

Mitchell A. Thornton, Theodore W. Manikas

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Embedded and real-time systems classes in traditional and distance education format.

Mitchell A. Thornton, Theodore W. Manikas, Phillip A. Laplante

Proceedings of the IEEE Frontiers in Education Conference, 2013

Built-in Self-Repair in a 3D die stack using programmable logic.

Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Integrated Circuit Channel Routing using a Pareto-Optimal Genetic Algorithm.

Theodore W. Manikas

J. Circuits Syst. Comput., 2012

Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams.

Theodore W. Manikas, David Y. Feinstein, Mitchell A. Thornton

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

2011

Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities.

Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010

An Electrical Engineering Summer Academy for Middle School and High School Students.

Peter G. LoPresti, Theodore W. Manikas, Jeff Kohlbeck

IEEE Trans. Educ., 2010

On-chip thermal optimisation by whitespace reallocation using a constrained particleswarm optimisation algorithm.

Debarshi Chatterjee, Theodore W. Manikas

IET Circuits Devices Syst., 2010

2009

A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths.

Kamran H. Sedighi, Theodore W. Manikas, Kaveh Ashenayi, Roger L. Wainwright

Int. J. Robotics Autom., 2009

2008

Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells.

Theodore W. Manikas, Dale Teeters

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2006

Evolving A Diverse Collection of Robot Path Planning Problems.

Daniel A. Ashlock, Theodore W. Manikas, Kaveh Ashenayi

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2004

Autonomous local path planning for a mobile robot using a genetic algorithm.

Kamran H. Sedighi, Kaveh Ashenayi, Theodore W. Manikas, Roger L. Wainwright, Heng-Ming Tai

Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2002

Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement.

Theodore W. Manikas, Gerald R. Kane

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002