Stephen Y. H. Su

According to our database1, Stephen Y. H. Su authored at least 51 papers between 1971 and 1997.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of two.

Timeline

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Bibliography

1997
Fault-Tolerant Array Processors Via Reconfiguration of Two-Level Redundancy Arrays.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

1991
Self-Diagnosis of Faelures in VLSI Tree Array Processors.
IEEE Trans. Computers, 1991

Distributed self-diagnosis of VLSI mesh array processors.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

1989
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy.
IEEE Trans. Computers, 1989

1988
A Functional Testing Method for Microprocessors.
IEEE Trans. Computers, 1988

Designs for Diagnosability and Reliability in VLSI Systems.
Proceedings of the Proceedings International Test Conference 1988, 1988

Fault Isolation in Grey Systems.
Proceedings of the Proceedings International Test Conference 1988, 1988

1986
Analysis of a Class of Recovery Procedures.
IEEE Trans. Computers, 1986

1985
The S-Algorithm: A Promising Solution for Systematic Functional Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

Detecting I/O and Internal Feedback Bridging Faults.
IEEE Trans. Computers, 1985

VLSI Functional Test Pattern Generation: A Design and Implementation.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique.
Proceedings of the Proceedings International Test Conference 1984, 1984

VLSI functional testing using critical path traces at hardware description language level.
Proceedings of the Fehlertolerierende Rechensysteme, 1984

Functional testing techniques for digital LSI/VLSI systems.
Proceedings of the 21st Design Automation Conference, 1984

IDAS: an integrated design automation system.
Proceedings of the American Federation of Information Processing Societies: 1984 National Computer Conference, 1984

1983
A Simplified Algorithm for Testing Microprocessors.
Proceedings of the Proceedings International Test Conference 1983, 1983

1982
Fault Diagnosis of MOS Combinational Networks.
IEEE Trans. Computers, 1982

A New Fault Model and Testing Technique for CMOS Devices.
Proceedings of the Proceedings International Test Conference 1982, 1982

Testing functional faults in VLSI.
Proceedings of the 19th Design Automation Conference, 1982

1981
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults.
IEEE Trans. Computers, 1981

Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits.
IEEE Trans. Computers, 1981

Testing Functional Faults in Digital Systems Described by Register Transfer Language.
Proceedings of the Proceedings International Test Conference 1981, 1981

State Diagram Approach for Functional Testing of Control Section.
Proceedings of the Proceedings International Test Conference 1981, 1981

1980
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures.
IEEE Trans. Computers, 1980

Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines.
IEEE Trans. Computers, 1980

Detecting bridging and stuck-at faults at input and output pins of standard digital components.
Proceedings of the 17th Design Automation Conference, 1980

1979
Reliability Analysis of <i>N</i>-Modular Redundancy Systems with Intermittent and Permanent Faults.
IEEE Trans. Computers, 1979

A survey of methods for intermittent fault analysis.
Proceedings of the 1979 International Workshop on Managing Requirements Knowledge, 1979

1978
A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults.
IEEE Trans. Computers, 1978

Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results.
IEEE Trans. Computers, 1978

A scheme for tolerating faulty data in real-time systems.
Proceedings of the IEEE Computer Society's Second International Computer Software and Applications Conference, 1978

1977
Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks.
IEEE Trans. Computers, 1977

Hardware Description Language Applications: An Introdiction and Prognosis.
Computer, 1977

Logic design automation of diagnosable MOS combinational logic networks.
Proceedings of the 14th Design Automation Conference, 1977

An overview of fault-tolerant digital system architecture.
Proceedings of the American Federation of Information Processing Societies: 1977 National Computer Conference, 1977

1976
Identification of Multiple Stuck-Type Faults in Combinational Networks.
IEEE Trans. Computers, 1976

1975
An introduction to CHDL (computer hardware description languages).
SIGARCH Comput. Archit. News, 1975

1974
Book review of Logic and logic design by B. Girling and H. G. Morning. International Textbook Company Limited 1973.
SIGARCH Comput. Archit. News, 1974

A survey of computer hardware description languages in the U.S.A.
Computer, 1974

Speculation on the future of design automation.
Proceedings of the 11th Design Automation Workshop, 1974

1973
Review of "Asynchronous Sequential Switching Circuits" by S. H. Unger.
IEEE Trans. Syst. Man Cybern., 1973

Review of "Fault Diagnosis of Digital Systems" by H. Y. Chang, E. G. Manning, and G. Metze.
IEEE Trans. Syst. Man Cybern., 1973

B73-12 Fault Detection in Digital Circuits.
IEEE Trans. Computers, 1973

An interactive design automation system.
Proceedings of the 10th Design Automation Workshop, 1973

1972
The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement.
IEEE Trans. Computers, 1972

Computer Minimization of Multivalued Switching Functions.
IEEE Trans. Computers, 1972

A New Approach to the Fault Location of Combinational Circuits.
IEEE Trans. Computers, 1972

1971
Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints.
IEEE Trans. Computers, 1971

A system modeling language translator.
Proceedings of the 8th Design Automation Workshop, 1971

The structure and operation of a design language compatible simulator.
Proceedings of the 8th Design Automation Workshop, 1971

A digital system modeling philosophy and design language.
Proceedings of the 8th Design Automation Workshop, 1971


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