Surya Bhattacharya

According to our database, Surya Bhattacharya authored at least 4 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling.

Surya Bhattacharya, Vempati Srinivasa Rao

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.

Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2015

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI).

Guruprasad Katti, S. W. Ho, Li Hong Yu, Songbai Zhang, Rahul Dutta, Roshan Weerasekera, Ka-Fai Chang, Jong-Kai Lin, Srinivasa Rao Vempati, Surya Bhattacharya

IEEE Des. Test, 2015

2011

Interconnect design and analysis for Through Silicon Interposers (TSIs).

Joseph Romen Cubillo, Roshan Weerasekera, Zaw Zaw Oo, En-Xiao Liu, Bob Conn, Surya Bhattacharya, Robert Patti

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011