Masaki Tsukude

According to our database, Masaki Tsukude authored at least 10 papers between 1989 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

400-MHz random column operating SDRAM techniques with self-skew compensation.

Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

1997

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's.

Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1997

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme.

Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto

IEEE J. Solid State Circuits, 1997

1996

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.

Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

IEEE J. Solid State Circuits, 1996

SOI-DRAM circuit technologies for low power high speed multigiga scale memories.

Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto

IEEE J. Solid State Circuits, 1996

1995

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs.

Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto

IEEE J. Solid State Circuits, November, 1995

1994

An experimental 256-Mb DRAM with boosted sense-ground scheme.

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

1993

Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.

Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima

IEEE Des. Test Comput., 1993

1992

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.

Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1989

A New Array Architecture for Parallel Testing in VLSI Memories.

Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima

Proceedings of the Proceedings International Test Conference 1989, 1989