Myeong-Jae Park
Orcid: 0000-0002-3552-8484
According to our database1,
Myeong-Jae Park
authored at least 16 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
A 2.5-V, 160-μJ-output piezoelectric energy harvester and power management IC for batteryless wireless switch (BWS) applications.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014
A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers.
Proceedings of the 2014 International Test Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits, 2013
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Fast and accurate event-driven simulation of mixed-signal systems with data supplementation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011