Taehyoun Oh
Orcid: 0000-0002-6574-0590
According to our database1,
Taehyoun Oh authored at least 12 papers
between 2010 and 2026.
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Bibliography
2026
A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving-71.6 dBc Fractional Spur in 65-nm CMOS Process.
IEEE Access, 2026
2025
A 8.9 to 10-GHz -97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process.
IEEE Access, 2025
2024
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process.
IEEE Access, 2024
2023
A Highly Integrated Radio Frequency Receiver RF CMOS Module for Core Body Temperature Thermometer.
IEEE Access, 2023
2022
Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2016
A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process.
Proceedings of the International SoC Design Conference, 2016
2014
IEICE Electron. Express, 2014
2013
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013
2012
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEEE J. Solid State Circuits, 2011
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010