Chulhyun Park

According to our database, Chulhyun Park authored at least 12 papers between 2009 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving-71.6 dBc Fractional Spur in 65-nm CMOS Process.

Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh

IEEE Access, 2026

2025

A 8.9 to 10-GHz -97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process.

Sangwon Kim, Kihoon Kwon, Minseo Park, Jinhyuk Ahn, Junseo Kim, Joonho Gil, Chulhyun Park, Yunseong Eo, Ramesh Harjani, Taehyoun Oh

IEEE Access, 2025

2024

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process.

Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun Seong Kim, Yun Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh

IEEE Access, 2024

2021

An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.

Soon-Jae Kweon, Joonho Gil, Chulhyun Park, Sein Oh, Yoontae Jung, Injun Choi, Song-I Cheon, Hung Phan Dang, Ja-Hyuck Koo, Geunhoe Kim, Sohmyung Ha, Minkyu Je

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test.

Tao Chen, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen

IEEE Trans. Instrum. Meas., 2020

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method.

Tao Chen, Chulhyun Park, Shravan K. Chaganti, José Silva-Martínez, Randall L. Geiger, Degang Chen

IEEE Trans. Instrum. Meas., 2020

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier.

Chulhyun Park, Tao Chen, Kyoohyun Noh, Dadian Zhou, Suraj Prakash, Mohammadhossein Naderi Alizadeh, Aydin I. Karsilayan, Degang Chen, Randall L. Geiger, José Silva-Martínez

IEEE Trans. Circuits Syst., 2020

2019

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.

Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.

Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2010

Outlier detection and countermeasure for hierarchical wireless sensor networks.

Yi-Ying Zhang, Han-Chieh Chao, Min Chen, Lei Shu, Chulhyun Park, Myong-Soon Park

IET Inf. Secur., 2010

Service Differentiation Using Mobile Femtocell Virtualization.

Eun Kyoung Paik, Sang-Hong Lee, Choongho Lee, Jinyoung Han, Chulhyun Park, Taekyoung Kwon, Yanghee Choi

Proceedings of the 7th IEEE Consumer Communications and Networking Conference, 2010

2009

Energy-Efficient Freshness Transmission Protocol in Wireless Sensor Networks.

Lin He, Yiying Zhang, Chulhyun Park, Myong-Soon Park

Proceedings of the International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, 2009