Joonho Gil
Orcid: 0000-0002-1789-6777
According to our database1,
Joonho Gil authored at least 7 papers
between 1998 and 2026.
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Bibliography
2026
A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving-71.6 dBc Fractional Spur in 65-nm CMOS Process.
IEEE Access, 2026
2025
A 8.9 to 10-GHz -97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process.
IEEE Access, 2025
2024
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process.
IEEE Access, 2024
2022
Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2005
Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier.
IEEE J. Solid State Circuits, 2005
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998