Luciano Volcan Agostini

According to our database1, Luciano Volcan Agostini authored at least 168 papers between 2004 and 2018.

Collaborative distances :
  • Dijkstra number2 of four.
  • Erdős number3 of four.

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Bibliography

2018
A reduced computational effort mode-level scheme for 3D-HEVC depth maps intra-frame prediction.
J. Visual Communication and Image Representation, 2018

Reference frame context-adaptive variable-length coder: a real-time hardware-friendly approach for lossless external memory bandwidth reduction in current video-coding systems.
J. Real-Time Image Processing, 2018

ASIC power-estimation accuracy evaluation: A case study using video-coding architectures.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Fast and energy-efficient HEVC transrating based on frame partitioning inheritance.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
Real-time scalable hardware architecture for 3D-HEVC bipartition modes.
J. Real-Time Image Processing, 2017

Energy-aware scheme for the 3D-HEVC depth maps prediction.
J. Real-Time Image Processing, 2017

Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Energy-efficient motion estimation with approximate arithmetic.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

Multiple early-termination scheme for TZ search algorithm based on data mining and decision trees.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

Characterizing energy consumption in software HEVC encoders: HM vs x265.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Energy evaluation of the HEVC decoding for different encoding configurations.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Complexity reduction by modes reduction in RD-list for intra-frame prediction in 3D-HEVC depth maps.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A multiplierless parallel HEVC quantization hardware for real-time UHD 8K video coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Edge-aware depth motion estimation - A complexity reduction scheme for 3D-HEVC.
Proceedings of the 25th European Signal Processing Conference, 2017

Depth modeling modes complexity control system for the 3D-HEVC video encoder.
Proceedings of the 25th European Signal Processing Conference, 2017

Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification.
Proceedings of the 25th European Signal Processing Conference, 2017

2016
Pareto-Based Method for High Efficiency Video Coding With Limited Encoding Time.
IEEE Trans. Circuits Syst. Video Techn., 2016

Fast intra prediction algorithm based on texture analysis for 3D-HEVC encoders.
J. Real-Time Image Processing, 2016

Complexity scalability for real-time HEVC encoders.
J. Real-Time Image Processing, 2016

DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard.
J. Electronic Imaging, 2016

Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A parallel Motion Estimation solution for heterogeneous System on Chip.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Squarer exploration for energy-efficient sum of squared differences.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Solutions for DMM-1 complexity reduction in 3D-HEVC based on gradient calculation.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy analisys of motion estimation memory transference on embedded processors.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy-efficient SATD for beyond HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fast H.264/AVC to HEVC transcoder based on data mining and decision trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Speedup-aware history-based tiling algorithm for the HEVC standard.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Rate-constrained successive elimination of Hadamard-based SATDs.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Pareto-based energy control for the HEVC encoder.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Coarse grain partial distortion elimination for Hadamard ME in HEVC.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Real-time simplified edge detector architecture for 3D-HEVC depth maps coding.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

3D-HEVC depth maps intra prediction complexity analysis.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Fast HEVC Encoding Decisions Using Data Mining.
IEEE Trans. Circuits Syst. Video Techn., 2015

DMMFast: a complexity reduction scheme for three-dimensional high-efficiency video coding intraframe depth map coding.
J. Electronic Imaging, 2015

Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

S-GMOF: A gradient-based complexity reduction algorithm for depth-maps intra prediction on 3D-HEVC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A real-time architecture for reference frame compression for high definition video coders.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Complexity reduction for the 3D-HEVC depth maps coding.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Encoding time control system for HEVC based on Rate-Distortion-Complexity analysis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fast mode selection algorithm based on texture analysis for 3D-HEVC intra prediction.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015

A multi-standard interpolation hardware solution for H.264 and HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014
Inter-view prediction of intra mode decision for high-efficiency video coding-based multiview video coding.
J. Electronic Imaging, 2014

Complexity reduction of depth intra coding for 3D video extension of HEVC.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

A complexity reduction algorithm for depth maps intra prediction on the 3D-HEVC.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Sample adaptive offset filter hardware design for HEVC encoder.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Four-step algorithm for early termination in HEVC inter-frame prediction based on decision trees.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

An efficient reference frame compression approach for video coding systems.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

HEVC Fractional Motion Estimation complexity reduction for real-time applications.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Configurable hardware design for the HEVC-based Adaptive Loop Filter.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Overview and quality analysis in 3D-HEVC emergent video coding standard.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Memory energy consumption reduction in video coding systems.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Memory bandwidth reduction for H.264 and HEVC encoders using lossless reference frame coding.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Complexity reduction for 3D-HEVC depth maps intra-frame prediction using simplified edge detector algorithm.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Classification-based early termination for coding tree structure decision in HEVC.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A low-complexity and lossless reference frame encoder algorithm for video coding.
Proceedings of the IEEE International Conference on Acoustics, 2014

Cost function optimization and its hardware design for the Sample Adaptive Offset of HEVC standard.
Proceedings of the 22nd European Signal Processing Conference, 2014

A method for early-splitting of HEVC inter blocks based on decision trees.
Proceedings of the 22nd European Signal Processing Conference, 2014

2013
Iterative random search: a new local minima resistant algorithm for motion estimation in high-definition videos.
Multimedia Tools Appl., 2013

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile.
J. Real-Time Image Processing, 2013

Hardware design for the 32×32 IDCT of the HEVC video coding standard.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

HEVC intra mode decision acceleration based on tree depth levels relationship.
Proceedings of the 30th Picture Coding Symposium, 2013

Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block.
Proceedings of the 30th Picture Coding Symposium, 2013

Constrained encoding structures for computational complexity scalability in HEVC.
Proceedings of the 30th Picture Coding Symposium, 2013

A lossless approach for external memory bandwidth reduction in video coding systems and its VLSI architecture.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo, 2013

A hardware friedly motion estimation algorithm for the emergent HEVC standard and its low power hardware design.
Proceedings of the IEEE International Conference on Image Processing, 2013

Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An adaptive workload management scheme for HEVC encoding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An energy-efficient hardware design for lossless reference frame compression in video coders.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Inter-view prediction of coding tree depth for HEVC-based multiview video coding.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

ES&IS: Enhanced Spread and Iterative Search hardware-friendly motion estimation algorithm for the HEVC Standard.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Computational complexity control for HEVC based on coding tree spatio-temporal correlation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Speeding up HEVC intra coding based on tree depth inter-levels correlation structure.
Proceedings of the 21st European Signal Processing Conference, 2013

Complexity control of HEVC through quadtree depth estimation.
Proceedings of Eurocon 2013, 2013

Coding Tree Depth Estimation for Complexity Reduction of HEVC.
Proceedings of the 2013 Data Compression Conference, 2013

Simplified HEVC FME Interpolation Unit Targeting a Low Cost and High Throughput Hardware Design.
Proceedings of the 2013 Data Compression Conference, 2013

Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
VLSI Design, 2012

Performance and Computational Complexity Assessment of High-Efficiency Video Encoders.
IEEE Trans. Circuits Syst. Video Techn., 2012

Evaluating two implementations of the component responsible for decoding video and audio in the Brazilian digital TV middleware.
Multimedia Tools Appl., 2012

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation.
Int. J. Reconfig. Comp., 2012

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.
Int. J. Reconfig. Comp., 2012

A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos.
Int. J. Reconfig. Comp., 2012

Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Adaptive coding tree for complexity control of high efficiency video encoders.
Proceedings of the 2012 Picture Coding Symposium, 2012

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

Motion Vectors Merging: Low Complexity Prediction Unit Decision Heuristic for the Inter-prediction of HEVC Encoders.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

High performance hardware architectures for the inverse Rotational Transform of the emerging HEVC standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Motion compensated tree depth limitation for complexity control of HEVC encoding.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Fast HEVC intra mode decision based on dominant edge evaluation and tree structure dependencies.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A high quality hardware friendly motion estimation algorithm focusing in HD videos.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Dynamic tree-depth adjustment for low power HEVC encoders.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Fast HEVC intra prediction mode decision based on EDGE direction information.
Proceedings of the 20th European Signal Processing Conference, 2012

2011
Complexity control of high efficiency video encoders for power-constrained devices.
IEEE Trans. Consumer Electronics, 2011

A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos.
Int. J. Reconfig. Comp., 2011

A comparative analysis of media processing component implementations for the Brazilian digital TV middleware.
IJITCC, 2011

Two fast multi-point search algorithms for high quality motion estimation in high resolution videos.
IJITCC, 2011

Two Novel Algorithms for High Quality Motion Estimation in High Definition Video Sequences.
Proceedings of the 24th SIBGRAPI Conference on Graphics, 2011

An efficient ME architecture for high definition videos using the new MPDS algorithm.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Algorithm and hardware design of a fast intra-frame mode decision module for h.264/AVC encoders.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

An efficient memory hierarchy for full search motion estimation on high definition digital videos.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Tests and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios.
Proceedings of the 5th FTRA International Conference on Multimedia and Ubiquitous Engineering, 2011

A multilevel data reuse scheme for Motion Estimation and its VLSI design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A real time HDTV motion estimation architecture for the new MPDS algorithm.
Proceedings of EUROCON 2011, 2011

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding.
Proceedings of the 48th Design Automation Conference, 2011

2010
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard.
CLEI Electron. J., 2010

Timing and interface communication analysis of H.264/AVC encoder using SystemC model.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A novel macroblock-level filtering upsampling architecture for H.264/AVC scalable extension.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Variable block size motion estimation architecture with a fast bottom-up decision mode and an integrated motion compensation targeting the H.264/AVC video coding standard.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Memory-aware multiple reference frame motion estimation for the H.264/AVC standard.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Homogeneity and distortion-based intra mode decision architecture for H.264/AVC.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering order.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Transforms and quantization design targeting the H.264/AVC intra prediction constraints.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction.
Proceedings of the International Conference on Image Processing, 2009

High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A multitransform architecture for the H.264/AVC standard and its design space exploration.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high throughput and low cost diamond search architecture for HDTV motion estimation.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs.
Microprocessors and Microsystems, 2007

Design and FPGA Prototyping of a H.264/AVC Main Profile.
J. Braz. Comp. Soc., 2007

FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Motion Compensation Hardware Accelerator Architecture for H.264/AVC.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

RIC Fast Adder and its Set Tolerant Implementation in FPGAs.
Proceedings of the FPL 2007, 2007

2006
Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.
Proceedings of the IFIP VLSI-SoC 2006, 2006

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

High throughput architecture for H.264/AVC forward transforms block.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

FPGA Based Architectures for H. 264/AVC Video Compression Standard.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Parallel color space converters for JPEG image compression.
Microelectronics Reliability, 2004

Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation.
Proceedings of the 2004 Design, 2004


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