Felipe A. Kuentzer

Orcid: 0000-0003-3177-372X

Affiliations:
  • University of Potsdam, Department of Computer Science, Germany
  • Innovations for High Performance Microelectronics (IHP), Frankfurt (Oder), Germany
  • Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil
  • University of Santa Cruz do Sul (UNISC), Department of Informatics, Brazil


According to our database1, Felipe A. Kuentzer authored at least 13 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

2022
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors.
J. Circuits Syst. Comput., December, 2022

2020
Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs.
IEEE Trans. Circuits Syst., 2020

Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2018
A DfT Insertion Methodology to Scannable Q-Flop Elements.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

An LSSD Compliant Scan Cell for Flip-Flops.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

On the reuse of timing resilient architecture for testing path delay faults in critical paths.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Optimized Design of an LSSD Scan Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Fault Classification of the Error Detection Logic in the Blade Resilient Template.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2014
Optimization and Analysis of Seriation Algorithm for Ordering Protein Networks.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Bioengineering, 2014

2009
FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test set.
Int. J. High Perform. Syst. Archit., 2009


  Loading...