Tiancheng Cao

Orcid: 0000-0002-7259-5192

According to our database1, Tiancheng Cao authored at least 15 papers between 2019 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
Step-Audio 2 Technical Report.
CoRR, July, 2025

Step-Audio-AQAA: a Fully End-to-End Expressive Large Audio Language Model.
CoRR, June, 2025

Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025

Step-Audio: Unified Understanding and Generation in Intelligent Speech Interaction.
CoRR, February, 2025

Step-Video-T2V Technical Report: The Practice, Challenges, and Future of Video Foundation Model.
CoRR, February, 2025

A Gait Data Compression and Reconstruction Framework for Edge Device using Low-Dimensional Attention Model with Autoencoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Neuromorphic FeRAM-Based Co-Design for Imaging Enhancement in Handheld Photoacoustic Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
DWT-PoolFormer: Discrete Wavelet Transform-based Quantized Parallel PoolFormer Network Implemented in FPGA for Wearable ECG Monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024

2023
RRAM-PoolFormer: A Resistive Memristor-based PoolFormer Modeling and Training Framework for Edge-AI Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

ECG Classification using Binary CNN on RRAM Crossbar with Nonidealities-Aware Training, Readout Compensation and CWT Preprocessing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

A Ternary Weight Mapping and Charge-mode Readout Scheme for Energy Efficient FeRAM Crossbar Compute-in-Memory System.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A Non-Idealities Aware Software-Hardware Co-Design Framework for Edge-AI Deep Neural Network Implemented on Memristive Crossbar.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Parasitic-Aware Modeling and Neural Network Training Scheme for Energy-Efficient Processing-in-Memory With Resistive Crossbar Array.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021
Parasitic-Aware Modelling for Neural Networks Implemented with Memristor Crossbar Array.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

2019
A Method of Ontology Evolution and Concept Evaluation Based on Knowledge Discovery in the Heavy Haul Railway Risk System.
Proceedings of the Collaborative Networks and Digital Transformation, 2019


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