Wang Ling Goh
Orcid: 0000-0001-7466-8941
According to our database1,
Wang Ling Goh
authored at least 104 papers
between 2005 and 2023.
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Bibliography
2023
A Nanowatt Temperature-Independent Tunable Active Capacitance Multiplier with DC Compensation in $0.13-\mu\mathrm{m}$ CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Sparsity Through Spiking Convolutional Neural Network for Audio Classification at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Classification of ECG Anomaly with Dynamically-biased LSTM for Continuous Cardiac Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
RRAM-PoolFormer: A Resistive Memristor-based PoolFormer Modeling and Training Framework for Edge-AI Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Battery-input Hysteretic Buck Converter with 430nA Quiescent Current and 5×10<sup>4</sup> Load Current Dynamic Range for Wearable Biomedical Devices.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Supervised Contrastive Pretrained ResNet with MixUp to Enhance Respiratory Sound Classification on Imbalanced and Limited Dataset.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
ECG Classification using Binary CNN on RRAM Crossbar with Nonidealities-Aware Training, Readout Compensation and CWT Preprocessing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A Convolved Self-Attention Model for IMU-based Gait Detection and Human Activity Recognition.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Energy Efficient Software-hardware Co-design of Quantized Recurrent Convolutional Neural Network for Continuous Cardiac Monitoring.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A Ternary Weight Mapping and Charge-mode Readout Scheme for Energy Efficient FeRAM Crossbar Compute-in-Memory System.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Non-Idealities Aware Software-Hardware Co-Design Framework for Edge-AI Deep Neural Network Implemented on Memristive Crossbar.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Parasitic-Aware Modeling and Neural Network Training Scheme for Energy-Efficient Processing-in-Memory With Resistive Crossbar Array.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
0.08mm<sup>2</sup> 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Design of Fully Differential Energy-Efficient Inverter-Based Low-Noise Amplifier for Ultrasound Imaging.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Parasitic-Aware Modelling for Neural Networks Implemented with Memristor Crossbar Array.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
A 3-MHz 17.3- $\mu$ W 0.015% Period Jitter Relaxation Oscillator With Energy Efficient Swing Boosting.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A TDM-Based 16-Channel AFE ASIC With Enhanced System-Level CMRR for Wearable EEG Recording With Dry Electrodes.
IEEE Trans. Biomed. Circuits Syst., 2020
An Integrated Multi-Channel Biopotential Recording Analog Front-End IC With Area-Efficient Driven-Right-Leg Circuit.
IEEE Trans. Biomed. Circuits Syst., 2020
Int. J. Comput. Vis., 2020
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-Based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing.
IEEE Trans. Ind. Electron., 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
A 1.6MHz Swing-Boosted Relaxation Oscillator with ±0.15%/V 23.4ppm/°C Frequency Inaccuracy using Voltage-to-Delay Feedback.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019
Proceedings of the IEEE VTS Asia Pacific Wireless Communications Symposium, 2019
2018
A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices.
Sensors, 2018
Proceedings of the 4th IEEE World Forum on Internet of Things, 2018
Proceedings of the 2018 IEEE International Conference on Service Operations and Logistics, and Informatics (SOLI), Singpapore, Singapore, July 31, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Rectifier-less Energy Harvesting Interface Circuit for Low-Voltage Piezoelectric Transducers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018
SqueezedText: A Real-Time Scene Text Recognition by Binary Convolutional Encoder-Decoder Network.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018
Feasibility of dictionary-based sparse coding for data compression in machine condition-based monitoring.
Proceedings of the 17th IEEE/ACIS International Conference on Computer and Information Science, 2018
2017
Enhanced active-feedback frequency compensation with on-chip-capacitor reduction feature for amplifiers with large capacitive load.
Int. J. Circuit Theory Appl., 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recording.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 12.77-MHz 31 ppm/°C On-Chip RC Relaxation Oscillator With Digital Compensation Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 9.84-73.2 nJ, 0.048 mm<sup>2</sup> time-domain impedance sensor that provides values of resistance and capacitance.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
A 12.4-kHz on-chip RC oscillator with comparator offset cancellation for PVT variation tolerance.
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Synchronous Electric Charge Extraction for low voltage Piezoelectric Energy Harvester array.
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Analysis of monolithic I/Q based impedance measurement circuits: Impact of non-ideal circuit effects on accuracies.
Proceedings of the International Symposium on Integrated Circuits, 2016
A 13.5-MHz relaxation oscillator with ±0.5% temperature stability for RFID application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Conference on Computing, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
A current-excited triple-time-voltage oversampling method for bio-impedance model for cost-efficient circuit system.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring.
IEEE J. Solid State Circuits, 2014
A three-topology based, wide input range switched-capacitor DC-DC converter with low-ripple and enhanced load line regulations.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detection.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Intrinsic Distortion of a Fully Differential BD-Modulated Class-D Amplifier With Analog Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Neural recording front-end IC using action potential detection and analog buffer with digital delay for data compression.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Proceedings of the 9th International Conference on Information, 2013
2012
A Dual-Feedforward Carrier-Modulated Second-Order Class-D Amplifier With Improved THD.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 60-V, >225°C Half-Bridge Driver for Piezoelectric Acoustic Transducer, on SOI CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE J. Solid State Circuits, 2012
A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning.
IEEE Trans. Very Large Scale Integr. Syst., 2009
2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005