Shuichi Sakai
According to our database1,
Shuichi Sakai
authored at least 79 papers
between 1985 and 2018.
Collaborative distances:
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Bibliography
2018
Bank-Aware Instruction Scheduler for a Multibanked Register File.
JIP, 2018
Estimating driver's readiness by understanding driving posture.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
2017
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency.
IEICE Transactions, 2017
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.
IEICE Transactions, 2017
Accelerating Integrity Verification on Secure Processors by Promissory Hash.
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017
2016
High-Accuracy Joint Position Estimation and Posture Detection System for Driving.
Proceedings of the Adjunct Proceedings of the 13th International Conference on Mobile and Ubiquitous Systems: Computing Networking and Services, 2016
"Stubborn" strategy to mitigate remaining cache misses.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Address Order Violation Detection with Parallel Counting Bloom Filters.
IEICE Transactions, 2015
An Inductive Method to Select Simulation Points.
Proceedings of the Third International Symposium on Computing and Networking, 2015
2014
A cloud architecture for protecting guest's information from malicious operators with memory management.
Proceedings of the Fourth ACM Conference on Data and Application Security and Privacy, 2014
2013
Register Indirect Jump Target Forwarding.
IEICE Transactions, 2013
2010
Register Cache System Not for Latency Reduction Purpose.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
2009
Low-Overhead Architecture for Security Tag.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009
String-Wise Information Flow Tracking against Script Injection Attacks.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009
Dependable VLSI: device, design and architecture: how should they cooperate?
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Ultra Dependable Processor.
IEICE Transactions, 2008
2007
Preventing timing errors on register writes: mechanisms of detections and recoveries.
SIGARCH Computer Architecture News, 2007
Musical part separation based on perceptual hierarchy.
Systems and Computers in Japan, 2007
Utilization of SECDED for soft error and variation-induced defect tolerance in caches.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Base Address Recognition with Data Flow Tracking for Injection Attack Detection.
Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006
SEVA: A Soft-Error- and Variation-Aware Cache Architecture.
Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006
2005
Associating semantically structured cooking videos with their preparation steps.
Systems and Computers in Japan, 2005
Cooking navi: assistant for daily cooking in kitchen.
Proceedings of the 13th ACM International Conference on Multimedia, 2005
Dynamic Estimation of Task Level Parallelism with Operating System Support.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2004
Multimedia Integration for Cooking Video Indexing.
Proceedings of the Advances in Multimedia Information Processing - PCM 2004, 5th Pacific Rim Conference on Multimedia, Tokyo, Japan, November 30, 2004
2003
Compilation of dictionaries for semantic attribute analysis of television news captions.
Systems and Computers in Japan, 2003
A note on greedy algorithms for the maximum weighted independent set problem.
Discrete Applied Mathematics, 2003
Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors.
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003
Compiler-Assisted Thread Level Control Speculation.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
Associating Cooking Video Segments with Preparation Steps.
Proceedings of the Image and Video Retrieval, Second International Conference, 2003
2002
CMP on SoC: Architect's View.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
An object detection method for describing soccer games from video.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002
2001
An attribute based news video indexing.
Proceedings of the 2001 ACM workshops on Multimedia: multimedia information retrieval, Ottawa, ON, Canada, September 30, 2001
Improving Conditional Branch Prediction on Speculative Multithreading Architectures.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001
2000
Scene identification in news video by character region segmentation.
Proceedings of the ACM Multimedia 2000 Workshops, Los Angeles, CA, USA, October 30, 2000
Associating cooking video with related textbook.
Proceedings of the ACM Multimedia 2000 Workshops, Los Angeles, CA, USA, October 30, 2000
Structural analysis of cooking preparation steps in Japanese.
Proceedings of the Fifth International Workshop on Information Retrieval with Asian Languages, 2000, Hong Kong, China, September 30, 2000
1999
Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams.
Proceedings of the 12th Annual ACM Symposium on User Interface Software and Technology, 1999
Associating video with related documents.
Proceedings of the 7th ACM International Conference on Multimedia '99, Orlando, FL, USA, October 30, 1999
Relating Graphical Features with Concept Classes for Automatic News Video Indexing.
Proceedings of the IJCAI-99 Workshop on Intelligent Information Integration, 1999
Inter-procedural Analysis for Parallelization of Java Programs.
Proceedings of the Parallel Computation, 1999
1997
Fine-Grain Multithreading with the EM-X Multiprocessor.
Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures, 1997
Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997
Virtual control channel and its application to the massively parallel computer RWC-1.
Proceedings of the Fourth International on High-Performance Computing, 1997
Parallel Execution of Radix Sort Program Using Fine-Grain Communication.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997
1996
Identifying the capability of overlapping computation with communication.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996
Multithread execution mechanisms on RICA-1 for massively parallel computation.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996
1995
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4.
Parallel Computing, 1995
Time Space Sharing Scheduling and Architectural Support.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 1995
The EM-X Parallel Computer: Architecture and Basic Performance.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995
A Macrotask-level Unlimited Speculative Execution on Multiprocessors.
Proceedings of the 9th international conference on Supercomputing, 1995
A prototype router for the massively parallel computer RWC-1.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
1994
Programming with Distributed Data Structure for EM-X Multiprocessor.
Proceedings of the Theory and Practice of Parallel Programming, 1994
Parallel bidirectional heuristic search on the EM-4 multiprocessor.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994
Nonnumeric search results on the EM-4 distributed-memory multiprocessor.
Proceedings of the Proceedings Supercomputing '94, 1994
Message-based efficient remote memory access on a highly parallel computer EM-X.
Proceedings of the International Symposium on Parallel Architectures, 1994
Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4.
Proceedings of the 8th International Symposium on Parallel Processing, 1994
EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994
Overview of RWC Massively Parallel Computer Project.
Proceedings of the Third International Symposium on High Performance Distributed Computing, 1994
1993
Evaluation of parallel execution performance by highly parallel computer EM-4.
Systems and Computers in Japan, 1993
Design and Implementation of a Circular Omega Network in the EM-4.
Parallel Computing, 1993
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993
Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation.
Proceedings of the 7th international conference on Supercomputing, 1993
EMC-Y: Parallel Processing Element Optimizing Communication and Computation.
Proceedings of the 7th international conference on Supercomputing, 1993
1992
Methodologies in development and testing of the dataflow machine EM-4.
Parallel Computing, 1992
A prototype of a highly parallel dataflow machine EM-4 and its preliminary evaluation.
Future Generation Comp. Syst., 1992
A priority forwarding scheme for real-time multistage interconnection networks.
Proceedings of the Real-Time Systems Symposium, 1992
Thread-based Programming for the EM-4 Hybrid Dataflow Machine.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992
Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem.
FGCS, 1992
1991
Load balancing by function distribution on the EM-4 prototype.
Proceedings of the Proceedings Supercomputing '91, 1991
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Prototype Implementation of a Highly Parallel Dataflow Machine EM-4.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Design and Implementation of a Versatile Interconnection Network in the EM-4.
Proceedings of the International Conference on Parallel Processing, 1991
1990
Dataflow computer development in Japan.
Proceedings of the 4th international conference on Supercomputing, 1990
1989
An Architecture of a Dataflow Single Chip Processor.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989
An Architectural Disgn of a Highly Parallel Dataflow Machine.
IFIP Congress, 1989
1986
Interconnection networks for bucket distribution on relational algebra machine GRACE.
Systems and Computers in Japan, 1986
1985
Interconnection network for bucket collection on relational algebra machine GRACE.
Systems and Computers in Japan, 1985