According to our database1, Toru Iwata authored at least 7 papers between 1996 and 2018.
Legend:Book In proceedings Article PhD thesis Other
An ultra-wide range (0.01-240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator.
IEICE Electron. Express, 2018
A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs.
IEICE Electron. Express, 2014
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration.
IEEE J. Solid State Circuits, 2011
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEICE Trans. Electron., 2005
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1997
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996