Taku Toshikawa

According to our database, Taku Toshikawa authored at least 5 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

An ultra-wide range (0.01-240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator.

Tsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Yutaka Terada, Toru Iwata

IEICE Electron. Express, 2018

2014

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2014

A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs.

Tsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Tomohiro Tsuchiya, Yutaka Terada, Tomoko Chiba, Keijiro Umehara, Toru Iwata, Takefumi Yoshikawa

IEICE Electron. Express, 2014

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation.

Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata

IEICE Trans. Electron., 2012