Toshiaki Sano

According to our database, Toshiaki Sano authored at least 6 papers between 1999 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A 6.05-Mb/mm² 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.

Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 5.92-Mb/mm² 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.

Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2014

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.

Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato

Proceedings of the Symposium on VLSI Circuits, 2014

2004

A cavity channel SESO embedded memory with low standby-power techniques.

Bryan Atwood, Tomoyuki Ishii, Takao Watanabe, Toshiyuki Mine, Norifumi Kameshiro, Toshiaki Sano, Kazuo Yano

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories.

Tomoyuki Ishii, Taro Osabe, Toshiyuki Mine, Toshiaki Sano, Bryan Atwood, Norifumi Kameshiro, Takao Watanabe, Kazuo Yano

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

1999

Single-electron memory for giga-to-tera bit storage.

Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki

Proc. IEEE, 1999