Tosiron Adegbija

Orcid: 0000-0002-2800-4834

According to our database1, Tosiron Adegbija authored at least 52 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks.
CoRR, 2024

PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine.
CoRR, 2024

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey.
IEEE Access, 2024

2023
Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research.
Proceedings of the IEEE International Conference on Acoustics, 2023

Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing.
J. Signal Process. Syst., 2022

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems.
Sustain. Comput. Informatics Syst., 2022

Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads.
Future Gener. Comput. Syst., 2022

A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Energy characterization of graph workloads.
Sustain. Comput. Informatics Syst., 2021

DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

2020
A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior.
IEEE Trans. Parallel Distributed Syst., 2020

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel Attacks.
IEEE Consumer Electron. Mag., 2020

Message from the Technical Program Chairs iSES 2020.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems.
IEEE Trans. Computers, 2019

ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors.
Proceedings of the International Symposium on Memory Systems, 2019

Energy and Performance Analysis of STTRAM Caches for Mobile Applications.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Bit-Wise and Multi-GPU Implementations of the DNA Recombination Algorithm.
Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Right-Provisioned IoT Edge Computing: An Overview.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Microprocessor Optimizations for the Internet of Things: A Survey.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

HERMIT: A Benchmark Suite for the Internet of Medical Things.
IEEE Internet Things J., 2018

<i>TaPT</i>: Temperature-Aware Dynamic Cache Optimization for Embedded Systems.
Comput., 2018

Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Workload Characterization of the SPEC CPU2017 Benchmark Suite.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

LARS: Logically adaptable retention time STT-RAM cache for embedded systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

AMELIA: An application of the Internet of Things for aviation safety.
Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018

2017
A Workload Characterization for the Internet of Medical Things (IoMT).
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exploiting Configurability as a Defense against Cache Side Channel Attacks.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Coding for Efficient Caching in Multicore Embedded Systems.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Application-Specific Autonomic Cache Tuning for General Purpose GPUs.
Proceedings of the 2017 International Conference on Cloud and Autonomic Computing, 2017

2016
Microprocessor Optimizations for the Internet of Things.
CoRR, 2016

Temperature-aware Dynamic Optimization of Embedded Systems.
CoRR, 2016

Phase-Based Dynamic Instruction Window Optimization for Embedded Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Phase-based Cache Locking for Embedded Systems.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Phase distance mapping: a phase-based cache tuning methodology for embedded systems.
Des. Autom. Embed. Syst., 2014

Dynamic Phase-Based Optimization of Embedded Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Analysis of cache tuner architectural layouts for multicore embedded systems.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Thermal-aware phase-based tuning of embedded systems.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Dynamic phase-based tuning for embedded systems using phase distance mapping.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012


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