Janet Roveda
Affiliations:- University of Arizona, Tucson, USA
According to our database1,
Janet Roveda
authored at least 99 papers
between 1996 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2023
TDSTF: Transformer-based Diffusion probabilistic model for Sparse Time series Forecasting.
CoRR, 2023
2022
IEEE Trans. Biomed. Circuits Syst., 2022
Pilot Study for Correlation of Heart Rate Variability and Dopamine Transporter Brain Imaging in Patients with Parkinsonian Syndrome.
Sensors, 2022
DeScoD-ECG: Deep Score-Based Diffusion Model for ECG Baseline Wander and Noise Removal.
CoRR, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Inter-Architecture Portability of Artificial Neural Networks and Side Channel Attacks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Methods and Analysis of Automated Trace Alignment Under Power Obfuscation in Side Channel Attacks.
J. Hardw. Syst. Secur., 2021
A Novel Low-Power Time Synchronization Algorithm Based on a Fractional Approach for Wireless Body Area Networks.
IEEE Access, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
Sequence-level Supervised Deep Neural Networks for Mitosis Event Detection in Time-Lapse Microscopy Images.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2020
2019
Cell Nuclei Detection and Segmentation for Computational Pathology Using Deep Learning.
Proceedings of the 2019 Spring Simulation Conference, 2019
Weakly Supervised Deep Learning for Detecting and Counting Dead Cells in Microscopy Images.
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019
2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Evaluation of the Complexity of Automated Trace Alignment using Novel Power Obfuscation Methods.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2016
Proceedings of the Modeling and Simulation in Medicine Symposium, 2016
2015
ACM Trans. Design Autom. Electr. Syst., 2015
A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching.
ACM Trans. Design Autom. Electr. Syst., 2015
Integr., 2015
Circuits Syst. Signal Process., 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Wearable sensor based stress management using integrated respiratory and ECG waveforms.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015
2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
A 60dBO 2.9 GHz 0.18 µm CMOS transimpedance amplifier for a fiber optic receiver application.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Conference on Computer Communications, 2014
2013
IEEE Trans. Emerg. Top. Comput., 2013
Effective signal region based analog mixed signal design considering variations and applications.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
OIRS: Outsourced Image Recovery Service From Comprehensive Sensing With Privacy Assurance.
Proceedings of the 20th Annual Network and Distributed System Security Symposium, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
2010
Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEICE Trans. Electron., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Physical Design, 2009
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A noniterative equivalent waveform model for timing analysis in presence of crosstalk.
ACM Trans. Design Autom. Electr. Syst., 2008
Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IET Circuits Devices Syst., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 International Symposium on Physical Design, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA).
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A non-iterative equivalent waveform model for timing analysis in presence of crosstalk.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS).
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design.
Proceedings of the 2005 Design, 2005
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
A perturbation-aware noise convergence methodology for high frequency microprocessors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
An efficient combinationality check technique for the synthesis of cyclic combinational circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 2004 International Symposium on Physical Design, 2004
Matrix pencil based realizable reduction for distributed interconnects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A new non-iterative model for switching window computation with crosstalk noise.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Stochastic analysis of interconnect performance in the presence of process variations.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
A linear fractional transform (LFT) based model for interconnect parametric uncertainty.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Realizable parasitic reduction for distributed interconnects using matrix pencil technique.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Switching Windows Computation in Presence of Crosstalk Noise.
Proceedings of the International Conference on VLSI, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
2000
Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks.
Proceedings of the 37th Conference on Design Automation, 2000
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources.
Proceedings of the 37th Conference on Design Automation, 2000
1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 Design, 1999
1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
1996
Simulation and sensitivity analysis of transmission line circuits by the characteristics method.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996