Travis Meade

According to our database1, Travis Meade authored at least 18 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Improving FSM State Enumeration Performance for Hardware Security with RECUT and REFSM-SAT.
CoRR, 2023

NetViz: A Tool for Netlist Security Visualization.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
A Structural and SAT Analysis of SANSCrypt.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2020
RELIC-FUN: Logic Identification through Functional Signal Comparisons.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.
IEEE Trans. Inf. Forensics Secur., 2019

Provably Secure Camouflaging Strategy for IC Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

SoC interconnection protection through formal verification.
Integr., 2019

NETA: when IP fails, secrets leak.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

RERTL: Finite State Transducer Logic Recovery at Register Transfer Level.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
The Old Frontier of Reverse Engineering: Netlist Partitioning.
J. Hardw. Syst. Secur., 2018

Microarchitectural Minefields: 4K-Aliasing Covert Channel and Multi-Tenant Detection in Iaas Clouds.
Proceedings of the 25th Annual Network and Distributed System Security Symposium, 2018

2017
IP protection through gate-level netlist security enhancement.
Integr., 2017

Revisit sequential logic obfuscation: Attacks and defenses.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

AppSAT: Approximately deobfuscating integrated circuits.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Gate-level netlist reverse engineering for hardware security: Control logic register identification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Netlist reverse engineering for high-level functionality reconstruction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016


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