Raj Gautam Dutta

Orcid: 0000-0002-5686-5666

According to our database1, Raj Gautam Dutta authored at least 24 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge.
CoRR, 2024

2023
LLM4SecHW: Leveraging Domain-Specific Large Language Model for Hardware Debugging.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
Design and Analysis of Secure Distributed Estimator for Vehicular Platooning in Adversarial Environment.
IEEE Trans. Intell. Transp. Syst., 2022

2021
On Sensor Security in the Era of IoT and CPS.
SN Comput. Sci., 2021

2020
Fast Attack-Resilient Distributed State Estimator for Cyber-Physical Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Survey of Machine Learning Methods for Detecting False Data Injection Attacks in Power Systems.
CoRR, 2020

Protecting Platoons from Stealthy Jamming Attack.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019
SoC interconnection protection through formal verification.
Integr., 2019

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

Resilient Distributed Filter for State Estimation of Cyber-Physical Systems Under Attack.
Proceedings of the 2019 American Control Conference, 2019

2018
Security for safety: a path toward building trusted autonomous vehicles.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals.
IEEE Trans. Inf. Forensics Secur., 2017

Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems.
IEEE Trans. Inf. Forensics Secur., 2017

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation.
IEEE Trans. Inf. Forensics Secur., 2017

Estimation of Safe Sensor Measurements of Autonomous System Under Attack.
Proceedings of the 54th Annual Design Automation Conference, 2017

PCH framework for IP runtime security verification.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Quantifying trust in autonomous system under uncertainties.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Automatic RTL-to-Formal Code Converter for IP Security Formal Verification.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Scalable SoC trust verification using integrated theorem proving and model checking.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

Pre-silicon security verification and validation: a formal perspective.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2012
Synthesis of insulin pump controllers from safety specifications using Bayesian model validation.
Int. J. Bioinform. Res. Appl., 2012

Parameter discovery for stochastic biological models against temporal behavioral specifications using an SPRT based Metric for simulated annealing.
Proceedings of the IEEE 2nd International Conference on Computational Advances in Bio and Medical Sciences, 2012


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