Tuan Thanh Ta

Orcid: 0000-0002-7703-372X

According to our database1, Tuan Thanh Ta authored at least 19 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE.
IEEE J. Solid State Circuits, 2020

5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.
IEEE J. Solid State Circuits, 2018

An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 3.2mA-RX 3.5mA-TX Fully Integrated SoC for Bluetooth Low Energy System.
IEICE Trans. Electron., 2017

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

1/2<i>f<sub>s</sub></i> Direct RF Under Sampling Receiver for Multi Channel Satellite Systems.
IEICE Trans. Electron., 2015

A Calibrationless Si-CMOS 5-bit Baseband Phase Shifter Using a Fixed-Gain-Amplifier Matrix.
IEICE Trans. Electron., 2013

A 5 GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit.
IEICE Trans. Electron., 2010

5GHz band low phase noise Si-CMOS oscillator using FBAR.
IEICE Electron. Express, 2010

5GHz Si-CMOS differential power amplifier module with directly connected dipole antenna.
IEICE Electron. Express, 2008