Masanori Furuta

According to our database, Masanori Furuta authored at least 36 papers between 2003 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Neuromorphic model of hippocampus place cells using an oscillatory interference technique for hardware implementation.

Zhaoqi Chen, Alia Nasrallah, Milad Alemohammad, Masanori Furuta, Ralph Etienne-Cummings

Neuromorph. Comput. Eng., December, 2022

2021

An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention.

Masanori Furuta, Koichiro Ban, Daisuke Kobayashi, Tomoyuki Shibata

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020

Velocity-Tuned Oscillators for NeuroSLAM and Spatial Navigation.

Alia Nasrallah, Zhaoqi Chen, Milad Alemohammad, Adyant Balaji, Adam B. Cellon, Masanori Furuta, Ralph Etienne-Cummings

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits.

Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura

IEEE Trans. Very Large Scale Integr. Syst., 2019

Velocity-Controlled Oscillators for Hippocampal Navigation on Spiking Neuromorphic Hardware.

Adam B. Cellon, Adebayo A. Eisape, Masanori Furuta, Ralph Etienne-Cummings

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.

Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.

Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura

IEEE J. Solid State Circuits, 2016

A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing.

Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA.

Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC.

Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.

Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB.

Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS.

Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors.

Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.

Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC.

Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal.

Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS.

Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier.

Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

All-digital background calibration for time-interleaved ADC using pseudo aliasing signal.

Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique.

Masanori Furuta, Mai Nozawa, Tetsuro Itakura

IEEE J. Solid State Circuits, 2011

A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier.

Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A 0.06mm² 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS.

Masanori Furuta, Mai Nozawa, Tetsuro Itakura

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

An area-efficient sampling rate converter using negative feedback technique.

Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters.

Masanori Furuta, Shoji Kawahito, Daisuke Miyazaki

IEEE Trans. Instrum. Meas., 2007

A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques.

Kazutaka Honda, Masanori Furuta, Shoji Kawahito

IEEE J. Solid State Circuits, 2007

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters.

Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito

IEEE J. Solid State Circuits, 2007

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits.

Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits.

Zheng Liu, Masanori Furuta, Shoji Kawahito

IEICE Trans. Electron., 2006

A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues.

Kazutaka Honda, Masanori Furuta, Shoji Kawahito

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters.

Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori, Masanori Furuta

IEEE J. Solid State Circuits, 2005

Low-Power Design of High-Speed A/D Converters.

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, Nobuhiro Kawai, Daisuke Miyazaki

IEICE Trans. Electron., 2005

A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors.

Masanori Furuta, Shoji Kawahito, Toru Inoue, Yukinari Nishikawa

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2003

A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture.

Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta

IEEE J. Solid State Circuits, 2003

A digitally skew correctable multi-phase clock generator using a master-slave DLL.

Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 75mW 10bit 120MSample/s parallel pipeline ADC.

Daisuke Miyazaki, Masanori Furuta, Shoji Kawahito

Proceedings of the ESSCIRC 2003, 2003