Masanori Furuta
According to our database1,
Masanori Furuta
authored at least 36 papers
between 2003 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
Neuromorphic model of hippocampus place cells using an oscillatory interference technique for hardware implementation.
Neuromorph. Comput. Eng., December, 2022
2021
An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Velocity-Controlled Oscillators for Hippocampal Navigation on Spiking Neuromorphic Hardware.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2017
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
2012
All-digital background calibration for time-interleaved ADC using pseudo aliasing signal.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique.
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters.
IEEE Trans. Instrum. Meas., 2007
A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques.
IEEE J. Solid State Circuits, 2007
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters.
IEEE J. Solid State Circuits, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits.
IEICE Trans. Electron., 2006
A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters.
IEEE J. Solid State Circuits, 2005
A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2003
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture.
IEEE J. Solid State Circuits, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the ESSCIRC 2003, 2003