Tung-Yang Chen

According to our database1, Tung-Yang Chen authored at least 10 papers between 1998 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2003
Substrate-triggered ESD protection circuit without extra process modification.
IEEE J. Solid State Circuits, 2003

2001
On-chip ESD protection design by using polysilicon diodes in CMOS process.
IEEE J. Solid State Circuits, 2001

Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Design on ESD Protection Circuit with Very Low and Constant Input Capacitance.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.
IEEE J. Solid State Circuits, 2000

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
ESD buses for whole-chip ESD protection.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
CMOS on-chip ESD protection design with substrate-triggering technique.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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