Chung-Yu Wu

According to our database1, Chung-Yu Wu authored at least 103 papers between 1985 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1998, "For contributions to implementation of analog neural network integrated circuits.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

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Bibliography

2019
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS.
IEEE Trans. on Circuits and Systems, 2019

Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.
IEEE Trans. Biomed. Engineering, 2019

A CMOS 256-Pixel Self-Photovoltaics-Powered Subretinal Prosthetic Chip with Wide Image Dynamic Range and Shared Electrodes and Its In Vitro Experimental Results on Rd1 Mice.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 2.36μW/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

The Design of CMOS Electrode-Tissue Impedance Measurement Circuit Using Differential Current Switch with CMFB Bias for Implantable Neuro-Modulation SoCs.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.
IEEE Trans. Biomed. Circuits and Systems, 2018

Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC).
J. Solid-State Circuits, 2018

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
J. Solid-State Circuits, 2018

The Design of CMOS 13.56-MHz High Efficiency 1×/3× 1.99V/6.29V Active Rectifier for Implantable Neuromodulation Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 1.97μ, W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Scoping Study on the Development of an Interactive Upper-Limb Rehabilitation System Framework for Patients with Stroke.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018

2017
A 16-channel CMOS chopper-stabilized analog front-end acquisition circuits for ECoG detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A gradient vector flow snake based multi-level morphological active contour algorithm.
Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017

Design considerations and clinical applications of closed-loop neural disorder control SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
The design of 8-channel CMOS area-efficient low-power current-mode analog front-end amplifier for EEG signal recording.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Novel Active Comb-Shaped Dry Electrode for EEG Measurement in Hairy Site.
IEEE Trans. Biomed. Engineering, 2015

An 8-channel power-efficient time-constant-enhanced analog front-end amplifier for neural signal acquisition.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A microfabricated coil for implantable applications of magnetic spinal cord stimulation.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

The design of CMOS self-powered 256-pixel implantable chip with on-chip photovoltaic cells and active pixel sensors for subretinal prostheses.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

An 8-channel chopper-stabilized analog front-end amplifier for EEG acquisition in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices.
J. Solid-State Circuits, 2014

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
J. Solid-State Circuits, 2014

A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013
Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor.
IEEE Trans. on Circuits and Systems, 2013

A CMOS Power-Efficient Low-Noise Current-Mode Front-End Amplifier for Neural Signal Recording.
IEEE Trans. Biomed. Circuits and Systems, 2013

A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A Low power 10bit 500kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable medical devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A MedRadio-band low-energy-per-bit 4-Mbps CMOS OOK receiver for implantable medical devices.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

A CMOS MedRadio-band low-power integer-N cascaded phase-locked loop for implantable medical SOCs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
A low-power current-mode front-end acquisition system for biopotential signal recording.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop.
IEICE Transactions, 2011

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

2010
Design and Analysis of a CMOS Ratio-Memory Cellular Nonlinear Network (RMCNN) Requiring No Elapsed Time.
IEEE Trans. on Circuits and Systems, 2010

Stability Analysis of Autonomous Ratio-Memory Cellular Nonlinear Networks for Pattern Recognition.
IEEE Trans. on Circuits and Systems, 2010

An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications.
IEICE Transactions, 2010

45-nm Planar bulk-CMOS 23-GHz LNAs with high-Q above-IC inductors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
The Design and Analysis of a CMOS Low-Power Large-Neighborhood CNN With Propagating Connections.
IEEE Trans. on Circuits and Systems, 2009

A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network.
Integr., 2009

A Low-Power K-Band CMOS Current-Mode Up-Conversion Mixer Integrated with VCO.
IEICE Transactions, 2009

A High Performance Linear Current Mode Image Sensor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power V-band Low Noise Amplifier Using 0.13-μm CMOS Technology.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

An Integrated 60-GHz Front-end Receiver with a Frequency Tripler Using 0.13-μm CMOS Technology.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

An efficient Compensation Method for Improving Luminance Uniformity of Organic Light Emitting Diode Panels.
Proceedings of the 2007 International Conference on Scientific Computing, 2007

2006
A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A 3.110.6 GHz CMOS Direct-Conversion Receiver for UWB Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers.
IEEE Trans. on Circuits and Systems, 2005

A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Novel low power high dynamic range all CMOS Current-mode AGC.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
New current-mode wave-pipelined architectures for high-speed analog-to-digital converters.
IEEE Trans. on Circuits and Systems, 2004

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications.
IEEE Trans. on Circuits and Systems, 2004

A low-power implantable Pseudo-BJT-based silicon retina with solar cells for artificial retinal prostheses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A CMOS focal-plane retinal sensor designed for shear motion detection.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for associative memory applications.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A low power design on diffusive interconnection large-neighborhood cellular nonlinear network for giga-scale system application.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Improvement of pattern learning and recognition capability in ratio-memory cellular neural networks with non-discrete-type Hebbian learning algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
The design of a CMOS IF bandpass amplifier with low sensitivity to process and temperature variations.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A new CMOS readout circuit for uncooled bolometric infrared focal plane arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

The new CMOS 2 V low-power IF fully differential Rm-C bandpass amplifier for RF wireless receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A compact CMOS 2 V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9 GHz RF transmitter applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Embedded Memory.
Proceedings of the VLSI Handbook., 1999

An improved BJT-based silicon retina with tunable image smoothing capability.
IEEE Trans. VLSI Syst., 1999

A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The design of high-performance 128×128 CMOS image sensors using new current-readout techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The design of CMOS cellular neural network (CNN) using the neuron-bipolar junction transistor (νBJT).
Proceedings of the International Joint Conference Neural Networks, 1999

1997
Guest Editorial.
IEEE Trans. Circuits Syst. Video Techn., 1997

Focal-plane-arrays and CMOS readout techniques of infrared imaging systems.
IEEE Trans. Circuits Syst. Video Techn., 1997

1996
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.
IEEE Trans. VLSI Syst., 1996

CMOS current-mode neural associative memory design with on-chip learning.
IEEE Trans. Neural Networks, 1996

Analog electronic cochlea design using multiplexing switched-capacitor circuits.
IEEE Trans. Neural Networks, 1996

1995
CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition.
VLSI Signal Processing, 1995

A 1.5V CMOS Balanced Differential Switched-Capacitor Filter with Internal Clock Boosters.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A 3-V 1-GHz Low-Noise Bandpass Amplifier.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud Filters.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Analog CMOS current-mode implementation of the feedforward neural network with on-chip learning and storage.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994
The Continuous-Time VHF Lowpass Filter Design Using Finite-Gain Current and Voltage Amplifiers and Special Q-Enhancement Circuit.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

VHF/UHF High-Q Bandpass Tunable Filters Design Using CMOS Inverter-Based Transresistnace Amplifiers.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

The Design of the CMOS Current-Mode General-Purpose Analog Processor.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
VHF Bandpass Filter Design Using CMOS Transresistance Amplifiers.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Ratio-independent and Gain-insensitive Algorithmic Analog-to-digital Converter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Chopper-stabilized Sigma-delta Modulator.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1990
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

1985
An Efficient Timing Model for CMOS Combinational Logic Gates.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985


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