Wen-Yu Lo

According to our database1, Wen-Yu Lo authored at least 9 papers between 1999 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
Investigating the Effects of Mobile Learning with Cross-Age Peer Tutoring in English Learning.
Proceedings of the IIAI 4th International Congress on Advanced Applied Informatics, 2015

2004
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003
Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC.
Microelectron. Reliab., 2003

2002
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process.
IEEE J. Solid State Circuits, 2000

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999


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