Tzu-Hsuan Hsu

According to our database, Tzu-Hsuan Hsu authored at least 11 papers between 2013 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Spurious-Free Lithium Niobate Bulk Acoustic Wave Resonator with Grounded-Ring Electrode.

Vakhtang Chulukhadze, Kristi Nguyen, Eric Stolt, Kilian Shambaugh, Weston Braun, Tzu-Hsuan Hsu, Osama Jameel, Juan Rivas-Davila, Ruochen Lu

CoRR, April, 2026

2025

Bimorph Lithium Niobate Piezoelectric Micromachined Ultrasonic Transducers.

Vakhtang Chulukhadze, Zihuan Liu, Ziqian Yao, Lezli Matto, Tzu-Hsuan Hsu, Nishanth Ravi, Xiaoyu Niu, Michael E. Liao, Mark S. Goorsky, Neal Hall, Ruochen Lu

CoRR, December, 2025

2023

A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device.

Wei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu

Proceedings of the IEEE International Memory Workshop, 2023

2022

Graph Attention Transformer for Unsupervised Multivariate Time Series Anomaly Detection.

Tzu-Hsuan Hsu, Yu-Chee Tseng, Jen-Jee Chen

Proceedings of MACLEAN: MAChine Learning for EArth ObservatioN Workshop co-located with the European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML/PKDD 2022), 2022

Using UTAUT, TTF, and PR integrating models to evaluate employees' acceptance and behavioral intention of PHM-based system in the military industry.

Tsung-Ti Chen, Yuan-Jen Chang, Tzu-Hsuan Hsu, He-Kai Hsu

Proceedings of the 2022 IEEE International Conference on Prognostics and Health Management, 2022

2021

Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator.

Hang-Ting Lue, Han-Wen Hu, Tzu-Hsuan Hsu, Po-Kai Hsu, Keh-Chung Wang, Chih-Yuan Lu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits.

Cheng-Lin Sung, Hang-Ting Lue, Wei-Chen Chen, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu

Proceedings of the IEEE International Memory Workshop, 2021

Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances.

Hang-Ting Lue, Tzu-Hsuan Hsu, Cheng-Lin Sung, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu

Proceedings of the IEEE International Memory Workshop, 2021

2014

Buffered clock tree synthesis considering self-heating effects.

Chung-Wei Lin, Tzu-Hsuan Hsu, Xin-Wei Shih, Yao-Wen Chang

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013

Using condition flag prediction to improve the performance of out-of-order processors.

Tzu-Hsuan Hsu, Ching-Wen Lin, Chung-Ho Chen

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Symmetrical buffered clock-tree synthesis with supply-voltage alignment.

Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013