Chih-Yuan Lu
According to our database1,
Chih-Yuan Lu
authored at least 22 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1995, "For contributions to semiconductor technology, and for leadership in the growth of the Taiwan integrated circuit industry.".
Timeline
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Bibliography
2023
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories.
Proceedings of the IEEE International Memory Workshop, 2023
A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device.
Proceedings of the IEEE International Memory Workshop, 2023
2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing.
Proceedings of the IEEE International Memory Workshop, 2022
2021
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits.
Proceedings of the IEEE International Memory Workshop, 2021
Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances.
Proceedings of the IEEE International Memory Workshop, 2021
2020
Statistical Analysis of Bit-Errors Distribution for Reliability of 3-D NAND Flash Memories.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Modeling of Apparent Activation Energy and Lifetime Estimation for Retention of 3D SGVC Memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Electrical method to localize the high-resistance of nanoscale CoSi2 word-line for OTP memories.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2015
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations.
IEEE J. Solid State Circuits, 2015
2006
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006