Kai-Yuan Chao

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Mask cost reduction with circuit performance consideration for self-aligned double patterning.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Simultaneous redundant via insertion and line end extension for yield optimization.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Optimal Double Via Insertion With On-Track Preference.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Multi-threaded collision-aware global routing with bounded-length maze routing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

On process-aware 1-D standard cell design.

[BibT_eX]

[DOI]

Hongbo Zhang

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Configurable multi-product floorplanning.

[BibT_eX]

[DOI]

Qiang Ma

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Wire shaping is practical.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

Spare-cell-aware multilevel analytical placement.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Fast Dummy-Fill Density Analysis With Coupling Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast and Optimal Redundant Via Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Optimal post-routing redundant via insertion.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

2007

Dummy fill density analysis with coupling constraints.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Is your layout density verification exact?: a fast exact algorithm for density calculation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Coupling-aware Dummy Metal Insertion for Lithography.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

An ECO routing algorithm for eliminating coupling-capacitance violations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Post-routing redundant via insertion and line end extension with via density consideration.

[BibT_eX]

[DOI]

Kuang-Yao Lee

Ting-Chi Wang

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

Simultaneous floor plan and buffer-block optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An ECO algorithm for eliminating crosstalk violations.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Physical Design, 2004

2003

Simultaneous floorplanning and buffer block planning.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

ECO algorithms for removing overlaps between power rails and signal wires.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Flip-Flop and Repeater Insertion for Early Interconnect Planning.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

1998

Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing.

[BibT_eX]

[DOI]

Shashidhar Thakur

VLSI Design, 1998

1995

An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing.

[BibT_eX]

[DOI]

Shashidhar Thakur

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Floorplanning for Low Power Designs.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Thermal placement for high-performance multichip modules.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Signal integrity optimization on the pad assignment for high-speed VLSI design.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Layer assignment for high-performance multi-chip modules.

[BibT_eX]

[DOI]