U. Shukla

According to our database, U. Shukla authored at least 4 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS.

Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla

IEEE Solid State Circuits Lett., 2025

2024

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.

Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology.

A. Chowdhury, J. Ma, Y. Li, J. Guo, X. Zhang, P. Ramakrishna, J. Gu, Y. Wang, L. Liang, U. Shukla, K. Mohammad, H. Yan, Y. Sun, M. Lin, Z. Jiang, F. Khan, M. Yeoh, C. Su, J. Ding, Matthew Baecher, S. Parker, H. Wang, M. Seymour, Michael Wielgos, Ken Chang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.

Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. Ramakrishna, S. Shi, S. Parker, U. Shukla, W. Kelly, W. Su, Z. Yu

Proceedings of the IEEE International Solid-State Circuits Conference, 2022