Michael Sorna

According to our database1, Michael Sorna authored at least 9 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012

Root cause identification of an hard-to-find on-chip power supply coupling fail.
Proceedings of the 2012 IEEE International Test Conference, 2012

2005
10+ gb/s 90-nm CMOS serial link demo in CBGA package.
IEEE J. Solid State Circuits, 2005

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization.
IEEE J. Solid State Circuits, 2005

2004
10+ Gb/s 90nm CMOS serial link demo in CBGA package.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems.
IEEE J. Solid State Circuits, 2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev., 2003

2002
40-Gb/s circuits built from a 120-GHz f<sub>T</sub> SiGe technology.
IEEE J. Solid State Circuits, 2002


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