Michael Sorna

According to our database, Michael Sorna authored at least 12 papers between 2002 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS.

Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla

IEEE Solid State Circuits Lett., 2025

2024

A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring.

J. Gu, J. Ma, J. Guo, F. Guo, D. Liang, Y. Li, C. Shen, P. Gao, X. Zhang, J. Ding, Michael Sorna, H. Wang, C. Cui, J. Troupe, P. Metty, Ken Chang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.

Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.

Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. Ramakrishna, S. Shi, S. Parker, U. Shukla, W. Kelly, W. Su, Z. Yu

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2012

Root cause identification of an hard-to-find on-chip power supply coupling fail.

Franco Stellari, Thomas Cowell, Peilin Song, Michael Sorna, Zeynep Toprak Deniz, John F. Bulzacchelli, Nandita A. Mitra

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology.

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2005

10+ gb/s 90-nm CMOS serial link demo in CBGA package.

Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna

IEEE J. Solid State Circuits, 2005

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization.

Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes

IEEE J. Solid State Circuits, 2005

2004

10+ Gb/s 90nm CMOS serial link demo in CBGA package.

Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems.

Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman

IEEE J. Solid State Circuits, 2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.

Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer

IBM J. Res. Dev., 2003

2002

40-Gb/s circuits built from a 120-GHz f_T SiGe technology.

Greg G. Freeman, Mounir Meghelli, Young Kwark, Steven Zier, Alexander V. Rylyakov, Michael Sorna, Todd Tanji, Oswin M. Schreiber, Keith Walter, Jae-Sung Rieh, Basanth Jagannathan, Alvin J. Joseph, Seshadri Subbanna

IEEE J. Solid State Circuits, 2002